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| mixed signal isp flash mcu family c8051f70x/71x rev. 1.0 7/10 copyright ? 2010 by silicon laboratories c8051f70x/71x capacitance to digital converter - supports buttons, sliders, wheels, capacitive prox- imity, and touch screen sensing - up to 38 input channels - fast 40 s per channel conversion time - 12, 13, 14, or 16-bit output - auto-scan and wake-on-touch - auto-accumulate 4, 8, 16, 32, or 64 samples 10-bit analog to digital converter - up to 500 ksps - up to 16 external single-ended inputs - vref from on-chip vref, external pin or v dd - internal or external start of conversion source - built-in temperature sensor analog comparator - programmable hysteresis and response time - configurable as interrupt or reset source on-chip debug - on-chip debug circuitry facilitates full speed, non- intrusive in-system debug (no emulator required) - provides breakpoints, single stepping, inspect/modify memory and registers - superior performance to emulation systems using ice-chips, target pods, and sockets - low cost, complete development kit supply voltage 1.8 to 3.6 v - built-in voltage supply monitor high-speed 8051 c core - pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks - up to 25 mips throughput with 25 mhz clock - expanded interrupt handler memory - 512 bytes internal data ram (256 + 256) - up to 16 kb flash; in-system programmable in 512- byte sectors - up to 32-byte data eeprom digital peripherals - up to 54 port i/o with high sink current - hardware enhanced uart, smbus? (i 2 c compati- ble), and enhanced spi? serial ports - four general purpose 16-bit counter/timers - 16-bit programmable counter array (pca) with 3 capture/compare modules and enhanced pwm functionality - real time clock mode using timer and crystal clock sources - 24.5 mhz 2% oscillator supports crystal-less uart operation - external oscillator: crystal, rc, c, or clock (1 or 2 pin modes) - can switch between clock s ources on-the-fly; useful in power saving modes 64-pin tqfp, 48-pin tqfp, 48-pin qfn, 32-pin qfn, 24-pin qfn temperature range: ?40 to +85 c analog peripherals 16 kb isp flash 512 b ram por debug circuitry flexible interrupts 8051 cpu (25 mips) digital i/o 24.5 mhz precision internal oscillator high-speed controller core crossbar voltage comparator + ? wdt uart smbus pca timer 0 timer 1 timer 2 timer 3 port 0 spi 10-bit 500 ksps adc temp sensor a m u x port 1 port 2 port 3 port 4 port 5 port 6.0 ? 6.5 32 b eeprom ext. memory i/f capacitive sense
c8051f70x/71x 2 rev. 1.0 rev. 1.0 3 c8051f70x/71x table of contents 1. system overview ........ .................................................................................. ........... 17 2. ordering information ....... ............................................................................. ........... 26 3. pin definitions........... .................................................................................. ............. 28 4. tqfp-64 package specifi cations ............... ................................................. ........... 37 5. tqfp-48 package specifi cations ............... ................................................. ........... 39 6. qfn-48 package specifications ..... ............................................................. ........... 41 7. qfn-32 package specifications ..... ............................................................. ........... 43 8. qfn-24 package specifications ..... ............................................................. ........... 45 9. electrical characteristics ......... .................................................................. ............. 47 9.1. absolute maximum specificat ions................ .......................................... ........... 47 9.2. electrical characteri stics ................ ........................................................ ........... 48 10. 10-bit adc (adc0) ................ ...................................................................... ........... 55 10.1. output code formatting ..... .................................................................. ........... 56 10.2. 8-bit mode ............ ................................................................................ ........... 56 10.3. modes of operation . ............................................................................. ........... 56 10.3.1. starting a conver sion........... ........................................................ ........... 56 10.3.2. tracking modes...... ...................................................................... ........... 57 10.3.3. settling time requirement s........................................................... ......... 58 10.4. programmable window detect or............. ............................................. ........... 62 10.4.1. window detect or example.......... ................................................. ........... 64 10.5. adc0 analog multiplexer ...... ............................................................... ........... 65 11. temperature sensor ............... .................................................................. ............. 67 11.1. calibration ............ ................................................................................ ........... 67 12. voltage and ground reference options........... .......................................... ......... 69 12.1. external voltage references ................... ............................................. ........... 70 12.2. internal voltage reference options ........... .......................................... ........... 70 12.3. analog ground reference....... ............................................................. ........... 70 12.4. temperature sensor enable ... ............................................................. ........... 70 13. voltage regulator (reg0) ........ .................................................................. ........... 72 14. comparator0.............. .................................................................................. ........... 74 14.1. comparator multiplexer ...... .................................................................. ........... 78 15. capacitive sense (cs0) . ............................................................................. ........... 80 15.1. configuring port pins as capacitive sense inputs ....... ............... ........... ......... 81 15.2. cs0 gain adjustment ......... .................................................................. ........... 81 15.3. capacitive sense start-of-conversion sour ces ................................ ............. 81 15.4. automatic scanning..... ......................................................................... ........... 83 15.5. cs0 comparator...... ............................................................................. ........... 84 15.6. cs0 conversion accumulator . ............................................................. ........... 85 15.7. cs0 pin monitor ...... ............................................................................. ........... 86 15.8. adjusting cs0 for special si tuations................ ................................. ............. 87 15.9. capacitive sense multiplexe r .................. ............................................. ........... 96 16. cip-51 microcontroller.............. .................................................................. ........... 98 16.1. instruction set....... ................................................................................ ........... 99 c8051f70x/71x 4 rev. 1.0 16.1.1. instruction and cpu timing ............... .......................................... ........... 99 16.2. cip-51 register descriptions .. ............................................................. ......... 104 17. memory organization .... ............................................................................. ......... 108 17.1. program memory....... ........................................................................... ......... 109 17.1.1. movx instruction and program memory .. ................................. ........... 109 17.2. eeprom memory ....... ......................................................................... ......... 109 17.3. data memory ........... ............................................................................. ......... 109 17.3.1. internal ram ..... ........................................................................... ......... 109 17.3.1.1. general purpose regi sters ................ ................................. ......... 110 17.3.1.2. bit addressable locat ions ............. .............. ............... .................. 110 17.3.1.3. stack ........... ...................................................................... ......... 110 18. external data memory interface and on-c hip xram ......... ............ .................. 111 18.1. accessing xram......... ......................................................................... ......... 111 18.1.1. 16-bit movx example ..... ............... ............................................. ......... 111 18.1.2. 8-bit movx exam ple ............... .................................................. ........... 111 18.2. configuring the external me mory interface ....... ................................. ........... 112 18.3. port configuration.... ............................................................................. ......... 112 18.4. multiplexed a nd non-multiplexed selection ........... ............................... ......... 115 18.4.1. multiplexed confi guration............................................................. ......... 115 18.4.2. non-multiplexed configuration............. ................................................. 116 18.5. memory mode selection........ ............................................................... ......... 117 18.5.1. internal xram only ...... ............................................................... ......... 117 18.5.2. split mode without bank se lect............................ ............... .................. 117 18.5.3. split mode with bank sele ct............... .......................................... ......... 118 18.5.4. external only..... ........................................................................... ......... 118 18.6. timing .......... ....................................................................................... ......... 118 18.6.1. non-multiplexed mode ................ ................................................. ......... 120 18.6.1.1. 16-bit movx: emi0 cf[4:2] = 101, 110, or 111. ................. ........... 120 18.6.1.2. 8-bit movx withou t bank select: emi0cf[4 :2] = 101 or 111 ....... 121 18.6.1.3. 8-bit movx with ba nk select: emi0cf[4:2] = 110 .............. ......... 122 18.6.2. multiplexed mode ... ...................................................................... ......... 123 18.6.2.1. 16-bit movx: emi0 cf[4:2] = 001, 010, or 011. ................. ........... 123 18.6.2.2. 8-bit movx withou t bank select: emi0cf[4 :2] = 001 or 011 ....... 124 18.6.2.3. 8-bit movx with ba nk select: emi0cf[4:2] = 010 .............. ......... 125 19. in-system device identification ................................................................. ......... 128 20. special function registers...... .................................................................. ......... 130 21. interrupts ............ ......................................................................................... ......... 137 21.1. mcu interrupt sour ces and vectors........... .......................................... ......... 138 21.1.1. interrupt priorities....... .................................................................. ......... 138 21.1.2. interrupt latency ............. ............................................................. ......... 138 21.2. interrupt register descripti ons .............. ............................................... ......... 140 21.3. int0 and int1 external interrupts....... ................................................. ......... 146 22. flash memory.............. ................................................................................ ......... 148 22.1. programming the flash memo ry ............... .......................................... ......... 148 22.1.1. flash lock and key functi ons ............... .............. ............... .................. 148 rev. 1.0 5 c8051f70x/71x 22.1.2. flash erase procedure ..... ........................................................... ......... 148 22.1.3. flash write procedure ..... ............... ............................................. ......... 149 22.2. non-volatile data storage .. .................................................................. ......... 149 22.3. security options ...... ............................................................................. ......... 149 22.4. flash write and erase guidel ines .............. .......................................... ......... 150 22.4.1. vdd maintenance and t he vdd monitor ...... ............................... ......... 151 22.4.2. pswe maintenance ............. ........................................................ ......... 151 22.4.3. system clock ...... ......................................................................... ......... 152 23. eeprom ............. ......................................................................................... ......... 155 23.1. ram reads and writes ........... ............................................................. ......... 155 23.2. auto increment ................. .................................................................. ........... 155 23.3. interfacing with th e eeprom.............. ................................................. ......... 155 23.4. eeprom security ..... ........................................................................... ......... 156 24. power management modes...... .................................................................. ......... 160 24.1. idle mode....... ....................................................................................... ......... 160 24.2. stop mode ............... ............................................................................. ......... 161 24.3. suspend mode .......... ........................................................................... ......... 161 25. reset sources ........... .................................................................................. ......... 163 25.1. power-on reset ...... ............................................................................. ......... 164 25.2. power-fail reset / vdd moni tor .................... .............. ............... .................. 165 25.3. external reset ................ ...................................................................... ......... 166 25.4. missing clock detector reset . ............................................................. ......... 166 25.5. comparator0 reset ............ .................................................................. ......... 167 25.6. watchdog timer reset ......................................................................... ......... 167 25.7. flash error reset .... ............................................................................. ......... 167 25.8. software reset ........ ............................................................................. ......... 167 26. watchdog timer............. ............................................................................. ......... 169 26.1. enable/reset wdt............. .................................................................. ......... 169 26.2. disable wdt ........... ............................................................................. ......... 169 26.3. disable wdt lockout............ ............................................................... ......... 169 26.4. setting wdt interval .......... .................................................................. ......... 169 27. oscillators and clock selection ............ .................................................. ........... 171 27.1. system clock selection...... .................................................................. ......... 171 27.2. programmable internal high-frequency (h-f) oscillator .. ................. ........... 173 27.3. external oscillator drive circuit........ .................................................. ........... 175 27.3.1. external crystal example. ............... ............................................. ......... 177 27.3.2. external rc example...... ............................................................. ......... 178 27.3.3. external capacitor exam ple............... .......................................... ......... 179 28. port input/output ...... .................................................................................. ......... 180 28.1. port i/o modes of operation. ................... ............................................. ......... 181 28.1.1. port pins configured fo r analog i/o.......... ................................. ........... 181 28.1.2. port pins configured fo r digital i/o.......... ................................. ........... 181 28.1.3. interfacing port i/o to 5 v logic ................ ................................. ........... 182 28.1.4. increasing port i/o drive strength ....... ................................................. 182 28.2. assigning port i/ o pins to analog and digital functi ons................. .............. 182 c8051f70x/71x 6 rev. 1.0 28.2.1. assigning port i/o pins to analog f unctions ............ ................. ........... 182 28.2.2. assigning port i/o pins to digital f unctions............ ............ .................. 184 28.2.3. assigning port i/o pins to external event trig ger functions.. .............. 184 28.3. priority crossbar decoder .. .................................................................. ......... 185 28.4. port i/o initializatio n ................ ............................................................. ......... 189 28.5. port match ............ ................................................................................ ......... 192 28.6. special function regist ers for accessing an d configuring port i/o ............. 194 29. cyclic redundancy check unit (crc0).......... .......................................... ......... 211 29.1. 16-bit crc algorit hm............... ............................................................. ......... 212 29.2. 32-bit crc algorit hm............... ............................................................. ......... 213 29.3. preparing for a crc calculatio n ................ .......................................... ......... 214 29.4. performing a crc calculation . ............... ............................................. ......... 214 29.5. accessing the crc0 result .... ............................................................. ......... 214 29.6. crc0 bit reverse feature.... ............................................................... ......... 218 30. smbus................. ......................................................................................... ......... 219 30.1. supporting document s ......................................................................... ......... 220 30.2. smbus configuration.......... .................................................................. ......... 220 30.3. smbus operation ...... ........................................................................... ......... 220 30.3.1. transmitter vs. receiver.. ............... ............................................. ......... 221 30.3.2. arbitration........ ............................................................................. ......... 221 30.3.3. clock low extensio n................ .................................................. ........... 221 30.3.4. scl low timeout... ...................................................................... ......... 221 30.3.5. scl high (smbus free) timeout ............... ................................. ......... 222 30.4. using the smbus..... ............................................................................. ......... 222 30.4.1. smbus configuration regi ster............. ................................................. 222 30.4.2. smb0cn control register ........................................................... ......... 226 30.4.2.1. software ack generat ion .................. ................................. ......... 226 30.4.2.2. hardware ack generat ion ............... ................................. ........... 226 30.4.3. hardware slave addre ss recognition ........ ................................. ......... 228 30.4.4. data register .... ........................................................................... ......... 231 30.5. smbus transfer modes......... ............................................................... ......... 232 30.5.1. write sequence (master) .. ........................................................... ......... 232 30.5.2. read sequence (master) ..... ........................................................ ......... 233 30.5.3. write sequence (slave) ... ............... ............................................. ......... 234 30.5.4. read sequence (slave) .... ........................................................... ......... 235 30.6. smbus status decodi ng................... .................................................. ........... 235 31. enhanced serial peripheral in terface (spi0) ......... ................................. ........... 241 31.1. signal descriptions.. ............................................................................. ......... 242 31.1.1. master out, slave in (m osi).............. .......................................... ......... 242 31.1.2. master in, slave out (m iso).............. .......................................... ......... 242 31.1.3. serial clock (sck ) ................................................................................ 242 31.1.4. slave select (nss) ....... ............................................................... ......... 242 31.2. spi0 master mode op eration .............. ................................................. ......... 242 31.3. spi0 slave m ode operation .................. ............................................... ......... 244 31.4. spi0 interrupt sources ....... .................................................................. ......... 245 rev. 1.0 7 c8051f70x/71x 31.5. serial clock phase and polari ty .............. ............................................. ......... 245 31.6. spi special function register s ............................................................ ......... 247 32. uart0 ................. ......................................................................................... ......... 254 32.1. enhanced baud rate generati on............ ............................................. ......... 255 32.2. operational modes ............. .................................................................. ......... 256 32.2.1. 8-bit uart ........ ........................................................................... ......... 256 32.2.2. 9-bit uart ........ ........................................................................... ......... 257 32.3. multiprocessor communication s ................ .......................................... ......... 258 33. timers ................... .................................................................................. .............. 26 2 33.1. timer 0 and timer 1 ... ............... ........................................................... ......... 264 33.1.1. mode 0: 13-bit counter/timer ............ .......................................... ......... 264 33.1.2. mode 1: 16-bit counter/timer ............ .......................................... ......... 265 33.1.3. mode 2: 8-bit counter/timer with auto-reload.... ............... .................. 265 33.1.4. mode 3: two 8-bit co unter/timers (timer 0 only)... ............................. 266 33.2. timer 2 .......... ....................................................................................... ......... 272 33.2.1. 16-bit timer with auto-rel oad................ .............. ............... .................. 272 33.2.2. 8-bit timers with auto - reload...................................................... ......... 273 33.3. timer 3 .......... ....................................................................................... ......... 278 33.3.1. 16-bit timer with auto-rel oad................ .............. ............... .................. 278 33.3.2. 8-bit timers with auto -reload...................................................... ......... 279 34. programmable counter array............ ........................................................ ......... 284 34.1. pca counter/timer ............ .................................................................. ......... 285 34.2. pca0 interrupt sources...... .................................................................. ......... 286 34.3. capture/compare modules ..... ............................................................. ......... 286 34.3.1. edge-triggered capture m ode.............................. ............... .................. 288 34.3.2. software timer (compare) mode................ ................................. ......... 289 34.3.3. high-speed output mode ............... ............................................. ......... 290 34.3.4. frequency output mode ............... ............................................... ......... 291 34.3.5. 8-bit, 9-bit, 10-bit and 11-bit pulse width modu lator modes .... ........... 292 34.3.5.1. 8-bit pulse width mo dulator mode......... ............................ ......... 292 34.3.5.2. 9/10/11-bit pulse width modulator mode........ ................. ........... 293 34.3.6. 16-bit pulse width modu lator mode.......... ................................. ......... 294 34.4. register descriptions for pc a0............. ............................................... ......... 295 35. c2 interface ............. .................................................................................. ........... 301 35.1. c2 interface registers........ .................................................................. ......... 301 35.2. c2ck pin sharing ... ............................................................................. ......... 304 document change list............... ...................................................................... ......... 305 contact information.......... ................................................................................ ......... 306 c8051f70x/71x 8 rev. 1.0 list of figures figure 1.1. c8051f700/1 block diagr am ............. .......................................... ......... 18 figure 1.2. c8051f702/3 block diagr am ............. .......................................... ......... 19 figure 1.3. c8051f704/5 block diagr am ............. .......................................... ......... 20 figure 1.4. c8051f706/07 bl ock diagram ............. .............. ............... ........... ......... 21 figure 1.5. c8051f708/09/10/11 blo ck diagram .......... ............................... ........... 22 figure 1.6. c8051f712/13/14/15 blo ck diagram .......... ............................... ........... 23 figure 1.7. c8051f716 blo ck diagram ......... ............................................... ........... 24 figure 1.8. c8051f717 blo ck diagram ......... ............................................... ........... 25 figure 3.1. c8051f7xx- gq tqfp64 pinout diagram (top view) .......... ................ 32 figure 3.2. c8051f7xx-gq qf p48 pinout diagram (t op view) ........... ............ ...... 33 figure 3.3. c8051f7xx-gm qf n48 pinout diagram (top view) ............... ............. 34 figure 3.4. c8051f716-gm qfn 32 pinout diagram (t op view) .......... ............ ...... 35 figure 3.5. c8051f717-gm qfn 24 pinout diagram (t op view) .......... ............ ...... 36 figure 4.1. tqfp-64 package drawi ng ............... .......................................... ......... 37 figure 4.2. tqfp-64 pcb land pattern ............. .......................................... ........... 38 figure 5.1. tqfp-48 package drawi ng ............... .......................................... ......... 39 figure 5.2. tqfp-48 pcb land pattern ............. .......................................... ........... 40 figure 6.1. qfn-48 package drawin g ...................... ................................. ............. 41 figure 6.2. qfn-48 pcb land pattern ............... .......................................... ........... 42 figure 7.1. qfn-32 package drawin g ...................... ................................. ............. 43 figure 7.2. qfn-32 recommended pcb land pattern ... ............................ ........... 44 figure 8.1. qfn-24 package drawin g ...................... ................................. ............. 45 figure 8.2. qfn-24 recommended pcb land pattern ... ............................ ........... 46 figure 10.1. adc0 functional blo ck diagram ............. ................................. ........... 55 figure 10.2. 10-bit adc track and conversion exam ple timing ......... ............ ...... 57 figure 10.3. adc0 equivalent inpu t circuits ............. ................................. ............. 58 figure 10.4. adc window compar e example: right-justified data .......... ............. 64 figure 10.5. adc window compare example: left-justified da ta ............ ............. 64 figure 10.6. adc0 multiplexer block diagram ..... .......................................... ......... 65 figure 11.1. temperature sensor transfer function .............. ............ ........... ......... 67 figure 11.2. temperature sensor error with 1-point calibrati on at 0 celsius ......... 68 figure 12.1. voltage reference functional block diagram ..... ............ ........... ......... 69 figure 14.1. comparator0 function al block diagram ............. ............ ........... ......... 74 figure 14.2. comparator hysteresis plot ............... .............. ............... ........... ......... 75 figure 14.3. comparator input mu ltiplexer block diagram ...... ............ ........... ......... 78 figure 15.1. cs0 block diagram ..... ............................................................. ........... 80 figure 15.2. auto-scan example ..... ............................................................. ........... 83 figure 15.3. cs0 multiplexer blo ck diagram ............. ................................. ............. 96 figure 16.1. cip-51 block diagram .. ............... ............................................. ........... 98 figure 17.1. c8051f70x/71x memory map ................. ................................. ......... 108 figure 17.2. flash program memory m ap ............ ................................................. 109 figure 18.1. multiplexed configur ation example ......... ................................. ......... 115 figure 18.2. non-multiplexed conf iguration example ............. ............ .................. 116 rev. 1.0 9 c8051f70x/71x figure 18.3. emif operati ng modes .................. .......................................... ......... 117 figure 18.4. non-multiplexed 16- bit movx timing ..... ................................. ......... 120 figure 18.5. non-multiplexed 8- bit movx without bank sele ct timing ................ 121 figure 18.6. non-multiplexed 8- bit movx with bank select ti ming .......... ........... 122 figure 18.7. multiplexed 16-bit movx timing ........... ................................. ........... 123 figure 18.8. multiplexed 8-bit movx without bank select ti ming ............. ........... 124 figure 18.9. multiplexed 8-bit mo vx with bank select timing ............................. 125 figure 23.1. eeprom block diagram ............... .......................................... ......... 155 figure 25.1. reset sources ........ .................................................................. ......... 163 figure 25.2. power-on and vdd monitor re set timing ...... ............... .................. 164 figure 27.1. oscillator op tions ............... ............................................................... 171 figure 27.2. external 32.768 kh z quartz crystal oscillat or connection diagram 178 figure 28.1. port i/o f unctional block diagram ............... ............................ ......... 180 figure 28.2. port i/o cell block diagram ........... .......................................... ......... 181 figure 28.3. port i/o overdrive cu rrent ................. .............. ............... .................. 182 figure 28.4. crossbar priority decoder?possi ble pin assignments .. .................. 186 figure 28.5. crossbar priority de coder in example configuration? no pins skipped ....... ............................................................... ......... 187 figure 28.6. crossbar priority de coder in example configuration? 3 pins skipped .......... ............................................................... ......... 188 figure 29.1. crc0 block diagram .. ............................................................. ......... 211 figure 30.1. smbus block diagram ............................................................. ......... 219 figure 30.2. typical smbus confi guration ................ ................................. ........... 220 figure 30.3. smbus transaction ..... ............................................................. ......... 221 figure 30.4. typical smbus scl ge neration .............. ................................. ......... 223 figure 30.5. typical master writ e sequence .............. ................................. ......... 232 figure 30.6. typical mast er read sequence ......... .............. ............... .................. 233 figure 30.7. typical slav e write sequence ........... .............. ............... .................. 234 figure 30.8. typical slave read s equence ................ ................................. ......... 235 figure 31.1. spi blo ck diagram ........... ........................................................ ......... 241 figure 31.2. multiple-master mo de connection diagram .......... ................. ........... 243 figure 31.3. 3-wire single master and single slav e mode connection diagram . 243 figure 31.4. 4-wire single master mode and slave mode connection diagram .. 244 figure 31.5. master mode data/clo ck timing ............. ................................. ......... 246 figure 31.6. slave mode data/clock timing (ckpha = 0) .. ............... .................. 246 figure 31.7. slave mode data/clock timing (ckpha = 1) .. ............... .................. 247 figure 31.8. spi mast er timing (ckpha = 0) . ............................................. ......... 251 figure 31.9. spi mast er timing (ckpha = 1) . ............................................. ......... 251 figure 31.10. spi slave ti ming (ckpha = 0) ........ .............. ............... .................. 252 figure 31.11. spi slave ti ming (ckpha = 1) ........ .............. ............... .................. 252 figure 32.1. uart0 block diagram ............ ................................................. ......... 254 figure 32.2. uart0 baud rate logi c ................ .......................................... ......... 255 figure 32.3. uart interconnect diagr am .............. .............. ............... .................. 256 figure 32.4. 8-bit uart timing diagram ........... .......................................... ......... 256 figure 32.5. 9-bit uart timing diagram ........... .......................................... ......... 257 c8051f70x/71x 10 rev. 1.0 figure 32.6. uart multi-proce ssor mode interconnect diagram ......... ................ 258 figure 33.1. t0 mode 0 block diagr am .............. .......................................... ......... 265 figure 33.2. t0 mode 2 block diagr am .............. .......................................... ......... 266 figure 33.3. t0 mode 3 block diagr am .............. .......................................... ......... 267 figure 33.4. timer 2 16-bi t mode block diagram .. .............. ............... .................. 272 figure 33.5. timer 2 8-bi t mode block diagram .. ................................................. 273 figure 33.7. timer 3 16-bi t mode block diagram .. .............. ............... .................. 278 figure 33.8. timer 3 8-bi t mode block diagram .. ................................................. 279 figure 33.9. timer 3 capt ure mode block diagram ........... ................................... 280 figure 34.1. pca block diagram ..... ............................................................. ......... 284 figure 34.2. pca counter/timer bl ock diagram ......... ................................. ......... 285 figure 34.3. pca interrupt block diagram ................ ................................. ........... 286 figure 34.4. pca capture mode diagram .............. .............. ............... .................. 288 figure 34.5. pca software time r mode diagram ....... ................................. ......... 289 figure 34.6. pca high-speed output mode diagram ...... ............................ ......... 290 figure 34.7. pca frequency output mode ............ .............. ............... .................. 291 figure 34.8. pca 8-bit pwm mode diagram ......... .............. ............... .................. 292 figure 34.9. pca 9, 10 and 11-bit pwm mode diagram .......... ................. ........... 293 figure 34.10. pca 16-bit pw m mode ........... ............................................... ......... 294 figure 35.1. typical c2ck pin shar ing .............. .......................................... ......... 304 rev. 1.0 11 c8051f70x/71x list of tables table 2.1. product selection guide ............... ............................................... ........... 27 table 3.1. pin definitions for t he c8051f70x/71x ....... ................................. ........... 28 table 4.1. tqfp-64 package dimens ions ........... .......................................... ......... 37 table 4.2. tqfp-64 pcb land patt ern dimensions ................. ................. ............. 38 table 5.1. tqfp-48 package dimens ions ........... .......................................... ......... 39 table 5.2. tqfp-48 pcb land patt ern dimensions ................. ................. ............. 40 table 6.1. qfn-48 package dimensi ons ............. .......................................... ......... 41 table 6.2. qfn-48 pcb land pattern dimensions .............. ............... ........... ......... 42 table 7.1. qfn-32 package dimensi ons ............. .......................................... ......... 43 table 7.2. qfn-32 pcb land pattern dimensions .............. ............... ........... ......... 44 table 8.1. qfn-24 package dimensi ons ............. .......................................... ......... 45 table 8.2. qfn-24 pcb land pattern dimensions .............. ............... ........... ......... 46 table 9.1. absolute maximum ratings ............... .......................................... ........... 47 table 9.2. global electrical char acteristics ............ .............. ............... ........... ......... 48 table 9.3. port i/o dc elec trical characteristics .............. ............................ ........... 49 table 9.4. reset electrical characteristics ......... .......................................... ........... 49 table 9.5. internal voltage regula tor electrical characteristi cs ................ ............. 50 table 9.6. flash electrical charac teristics ......... .......................................... ........... 50 table 9.7. internal high-frequency oscillator electrical char acteristics .... ............. 50 table 9.8. capacitive sense electr ical characteristics ................................ ........... 51 table 9.9. eeprom electrical c haracteristics .......... ................................. ............. 52 table 9.10. adc0 electrical char acteristics ........... .............. ............... ........... ......... 52 table 9.11. power management el ectrical characteristics ..... ............ ........... ......... 53 table 9.12. temperature sensor electrical characteristics .... ............ ........... ......... 53 table 9.13. voltage reference electrical charac teristics ....... ............ ........... ......... 53 table 9.14. comparator electrical characteristics .... ................................. ............. 54 table 15.1. gain setting vs. maximum capacitance and co nversion time ........... 81 table 15.2. operation with auto -scan and accumulate .......... ............ ........... ......... 85 table 16.1. cip-51 instruction set summary ............ ................................. ........... 100 table 18.1. ac parameters for external memory interface ..... ............ .................. 126 table 18.2. emif pinout (c8051f700/1/2/3/ 8/9 and c8051f710/1) ..... ................ 127 table 20.1. special function r egister (sfr) memory map .... ............ .................. 131 table 20.2. special function regist ers .............. .......................................... ......... 132 table 21.1. interrupt summary ... .................................................................. ......... 139 table 22.1. flash security summar y ................. .......................................... ......... 150 table 28.1. port i/o assignment for analog functions ........... ............ .................. 183 table 28.2. port i/o assignment for digital functions .......... ............... .................. 184 table 28.3. port i/o assignmen t for external event trigger functions ................. 184 table 29.1. example 16-bit crc ou tputs ............ ................................................. 212 table 29.2. example 32-bit crc ou tputs ............ ................................................. 213 table 30.1. smbus clock source selection .............. ................................. ........... 223 table 30.2. minimum sda setup and hold times ...... ................................. ......... 224 table 30.3. sources for hardwa re changes to smb0cn ......... ................. ........... 228 c8051f70x/71x 12 rev. 1.0 table 30.4. hardware address recognition examples (ehack = 1) ........ ........... 229 table 30.5. smbus status de coding: hardware ack disabled (ehack = 0) ...... 236 table 30.6. smbus status de coding: hardware ack enabl ed (ehack = 1) ...... 238 table 31.1. spi slave timing para meters ......... .......................................... ......... 253 table 32.1. timer settings for standard baud rates using the internal 24.5 mhz oscillator .. ................................. ........... 261 table 32.2. timer settings for standard baud rates using an external 22.1184 mhz oscillator ................................ ......... 261 table 34.1. pca timebase input op tions ............ ................................................. 285 table 34.2. pca0cpm and pca0 pwm bit settings for pca m odules ................. 287 rev. 1.0 13 c8051f70x/71x list of registers sfr definition 10.1. adc0cf: adc0 configuration ................. ............... ........... ......... 59 sfr definition 10.2. adc0h: adc0 data word msb ............... ............... ........... ......... 60 sfr definition 10.3. adc0l: adc0 data word lsb ............. ............................ ........... 60 sfr definition 10.4. adc0cn: adc0 control ................ ................................. ............. 61 sfr definition 10.5. adc0gth: adc0 greater-than da ta high byte ...... ............ ...... 62 sfr definition 10.6. adc0gtl: adc0 greater-than da ta low byte ...... ........... ......... 62 sfr definition 10.7. adc0lth: adc0 less-than data high byte ................. ............. 63 sfr definition 10.8. adc0ltl: ad c0 less-than data low byte ...................... ......... 63 sfr definition 10.9. adc0mx: am ux0 channel select .............. ............ ........... ......... 66 sfr definition 12.1. ref0cn: volt age reference control .......... ............ ........... ......... 71 sfr definition 13.1. reg0cn: vo ltage regulator control .......... ............ ........... ......... 73 sfr definition 14.1. cpt0cn: com parator0 control ....... ................................. ........... 76 sfr definition 14.2. cpt0md: co mparator0 mode selection ....... ................. ............. 77 sfr definition 14.3. cpt0mx: co mparator0 mux selection ...... ............ ........... ......... 79 sfr definition 15.1. cs0cn: capac itive sense control .. ................................. ........... 88 sfr definition 15.2. cs0c f: capacitive sense configuration ............................ ......... 89 sfr definition 15.3. cs0dh: capac itive sense data high byte .. ...................... ......... 90 sfr definition 15.4. cs0d l: capacitive sense data low byte ............ .............. ......... 90 sfr definition 15.5. cs0ss: capacitive sense auto-scan st art channel ..... ............. 91 sfr definition 15.6. cs0se: c apacitive sense auto-scan end channel ...... ............. 91 sfr definition 15.7. cs0thh: capacitive sense comparator threshold high byte ... 92 sfr definition 15.8. cs0thl: capacitive sense comparator threshold low byte .... 92 sfr definition 15.9. cs0pm: capa citive sense pin monitor ....... ............ ........... ......... 93 sfr definition 15.10. cs0md1: ca pacitive sense mode 1 ........... ................. ............. 94 sfr definition 15.11. cs0md2: ca pacitive sense mode 2 ........... ................. ............. 95 sfr definition 15.12. cs0mx: ca pacitive sense mux channel se lect .......... ............. 97 sfr definition 16.1. dpl: data po inter low byte ....... .............. ............... .................. 104 sfr definition 16.2. dph: data pointer high byte .. .......................................... ......... 104 sfr definition 16.3. sp: stack pointe r ................. ............................................. ......... 105 sfr definition 16.4. acc: accumulator ........ .................................................. ........... 105 sfr definition 16.5. b: b r egister ............. ........................................................ ......... 106 sfr definition 16.6. psw: program status word .......... ................................. ........... 107 sfr definition 18.1. emi0 cn: external memory interface co ntrol .............. .............. 113 sfr definition 18.2. emi0cf: exte rnal memory configuration .... ............ .................. 114 sfr definition 18.3. emi0tc: exte rnal memory timing control .. ............ .................. 119 sfr definition 19.1. hwid: hardwa re identification byte ......... ............... .................. 128 sfr definition 19.2. derivi d: derivative identification byte ............................ ......... 128 sfr definition 19.3. revi d: hardware revision i dentification byte ..... ..................... 129 sfr definition 20.1. sfrpage: sfr page ............ .......................................... ......... 132 sfr definition 21.1. ie: in terrupt enable .............. ............................................. ......... 140 sfr definition 21.2. ip: inte rrupt priority ............ ............................................... ......... 141 sfr definition 21.3. eie1: extended interrupt enable 1 .............. ............ .................. 142 sfr definition 21.4. eie2: extended interrupt enable 2 .............. ............ .................. 143 c8051f70x/71x 14 rev. 1.0 sfr definition 21.5. eip1: extended interrupt priority 1 ........... ............... .................. 144 sfr definition 21.6. eip2: extended interrupt priority 2 ........... ............... .................. 145 sfr definition 21.7. it01cf: int0 /int1 configuration .. ................................. ........... 147 sfr definition 22.1. psctl: prog ram store r/w control ................................ ......... 153 sfr definition 22.2. flkey: flas h lock and key ............ ................................. ......... 154 sfr definition 23.1. eeaddr: eepr om byte address .. ................................. ......... 156 sfr definition 23.2. eedata: eeprom byte data ................. ............... .................. 157 sfr definition 23.3. eecnt l: eeprom control ....... .............. ............... .................. 158 sfr definition 23.4. eekey: eeprom protect key ........ ................................. ......... 159 sfr definition 24.1. pcon: power control ............. .......................................... ......... 162 sfr definition 25.1. vdm0cn: vdd monitor control ...... ................................. ......... 166 sfr definition 25.2. rstsrc : reset source ......... .......................................... ......... 168 sfr definition 26.1. wdtcn: watc hdog timer control .............. ............ .................. 170 sfr definition 27.1. clksel: clock select ............ .......................................... ......... 172 sfr definition 27.2. oscicl: inte rnal h-f oscillator calibrati on ................ .............. 173 sfr definition 27.3. oscicn: inte rnal h-f oscillator control .. ............... .................. 174 sfr definition 27.4. oscxcn: exte rnal oscillator control ....... ............... .................. 176 sfr definition 28.1. xbr0: port i/ o crossbar register 0 ......... ............... .................. 190 sfr definition 28.2. xbr1: port i/ o crossbar register 1 ......... ............... .................. 191 sfr definition 28.3. p0mask: port 0 mask register ..... ................................. ........... 192 sfr definition 28.4. p0mat: port 0 match register ... .............. ............... .................. 193 sfr definition 28.5. p1mask: port 1 mask register ..... ................................. ........... 193 sfr definition 28.6. p1mat: port 1 match register ... .............. ............... .................. 194 sfr definition 28.7. p0: port 0 .... ...................................................................... ......... 195 sfr definition 28.8. p0mdin: port 0 input mode ........... ................................. ........... 195 sfr definition 28.9. p0mdout: po rt 0 output mode .... ................................. ........... 196 sfr definition 28.10. p0skip: port 0 skip ........... ............................................. ......... 196 sfr definition 28.11. p0drv: port 0 drive strength ................ ............... .................. 197 sfr definition 28.12. p1: port 1 .... .................................................................. ........... 197 sfr definition 28.13. p1mdin: port 1 input mode ......... ................................. ........... 198 sfr definition 28.14. p1mdout: po rt 1 output mode .... ................................. ......... 198 sfr definition 28.15. p1skip: port 1 skip ........... ............................................. ......... 199 sfr definition 28.16. p1drv: port 1 drive strength ................ ............... .................. 199 sfr definition 28.17. p2: port 2 .... .................................................................. ........... 200 sfr definition 28.18. p2mdin: port 2 input mode ......... ................................. ........... 200 sfr definition 28.19. p2mdout: po rt 2 output mode .... ................................. ......... 201 sfr definition 28.20. p2skip: port 2 skip ........... ............................................. ......... 201 sfr definition 28.21. p2drv: port 2 drive strength ................ ............... .................. 202 sfr definition 28.22. p3: port 3 .... .................................................................. ........... 202 sfr definition 28.23. p3mdin: port 3 input mode ......... ................................. ........... 203 sfr definition 28.24. p3mdout: po rt 3 output mode .... ................................. ......... 203 sfr definition 28.25. p3drv: port 3 drive strength ................ ............... .................. 204 sfr definition 28.26. p4: port 4 .... .................................................................. ........... 204 sfr definition 28.27. p4mdin: port 4 input mode ......... ................................. ........... 205 sfr definition 28.28. p4mdout: po rt 4 output mode .... ................................. ......... 205 rev. 1.0 15 c8051f70x/71x sfr definition 28.29. p4drv: port 4 drive strength ................ ............... .................. 206 sfr definition 28.30. p5: port 5 .... .................................................................. ........... 206 sfr definition 28.31. p5mdin: port 5 input mode ......... ................................. ........... 207 sfr definition 28.32. p5mdout: po rt 5 output mode .... ................................. ......... 207 sfr definition 28.33. p5drv: port 5 drive strength ................ ............... .................. 208 sfr definition 28.34. p6: port 6 .... .................................................................. ........... 208 sfr definition 28.35. p6mdin: port 6 input mode ......... ................................. ........... 209 sfr definition 28.36. p6mdout: po rt 6 output mode .... ................................. ......... 209 sfr definition 28.37. p6drv: port 6 drive strength ................ ............... .................. 210 sfr definition 29.1. crc0cn: crc0 control ............... ................................. ........... 215 sfr definition 29.2. crc0in: crc da ta input .............. ................................. ........... 216 sfr definition 29.3. crc0data: c rc data output ....... ................................. ......... 216 sfr definition 29.4. crc0auto: crc automatic control .......... ............ .................. 217 sfr definition 29.5. crc0cnt: crc automatic flash sector count ............ ........... 217 sfr definition 29.6. crc0flip: crc bi t flip ................ ................................. ........... 218 sfr definition 30.1. smb0cf: smbu s clock/configuration ........ ............ .................. 225 sfr definition 30.2. smb0cn: smbu s control .............. ................................. ........... 227 sfr definition 30.3. smb0 adr: smbus slave address ......... ................................... 229 sfr definition 30.4. smb0adm: smbus slave address mask .... ............ .................. 230 sfr definition 30.5. smb0dat: smbu s data ................ ................................. ........... 231 sfr definition 31.1. spi0cfg: spi 0 configuration ....... ................................. ........... 248 sfr definition 31.2. spi0cn: spi0 control ............ .......................................... ......... 249 sfr definition 31.3. spi0ckr: spi 0 clock rate ........... ................................. ........... 250 sfr definition 31.4. spi0dat: spi0 data ........... ............................................. ......... 250 sfr definition 32.1. scon0: serial port 0 control ..... .............. ............... .................. 259 sfr definition 32.2. sbuf0: seri al (uart0) port data buffer . ............... .................. 260 sfr definition 33.1. ckcon: clock control ............... .............. ............... .................. 263 sfr definition 33.2. tcon: timer c ontrol .............. .......................................... ......... 268 sfr definition 33.3. tmod: timer m ode ................ .......................................... ......... 269 sfr definition 33.4. tl0: timer 0 low byte ......... ............................................. ......... 270 sfr definition 33.5. tl1: timer 1 low byte ......... ............................................. ......... 270 sfr definition 33.6. th0: timer 0 high byte .............. .............. ............... .................. 271 sfr definition 33.7. th1: timer 1 high byte .............. .............. ............... .................. 271 sfr definition 33.8. tmr2cn: timer 2 control ............. ................................. ........... 275 sfr definition 33.9. tmr2rll: ti mer 2 reload register low byte ............... ........... 276 sfr definition 33.10. tmr2rlh: timer 2 reload regi ster high byte .... .................. 276 sfr definition 33.11. tmr2l: timer 2 low byte .... .......................................... ......... 277 sfr definition 33.12. tmr2h timer 2 high byte ........... ................................. ........... 277 sfr definition 33.13. tmr3cn: timer 3 control .... .......................................... ......... 281 sfr definition 33.14. tmr3rll: timer 3 reload regist er low byte ...... .................. 282 sfr definition 33.15. tmr3rlh: timer 3 reload regi ster high byte .... .................. 282 sfr definition 33.16. tmr3l: timer 3 low byte .... .......................................... ......... 283 sfr definition 33.17. tmr3h timer 3 high byte ........... ................................. ........... 283 sfr definition 34.1. pca0cn: pca c ontrol ........... .......................................... ......... 295 sfr definition 34.2. pca0md: pca mo de ............. .......................................... ......... 296 c8051f70x/71x 16 rev. 1.0 sfr definition 34.3. pca0pwm: pca pwm configuration ......... ............ .................. 297 sfr definition 34.4. pca0cpmn : pca capture/compare mode .. ................. ........... 298 sfr definition 34.5. pca0l: pca counter/timer low byte ........ ............ .................. 299 sfr definition 34.6. pca0h: pca counter/timer high byte ....... ............ .................. 299 sfr definition 34.7. pca0cpln: pca capture module low byte . ................. ........... 300 sfr definition 34.8. pca0cphn: pca capture module high byte ................ ........... 300 c2 register definition 35.1. c2ad d: c2 address ....... .............. ............... .................. 301 c2 register definition 35.2. deviceid: c2 device id .............. ............... .................. 302 c2 register definition 35.3. revid: c2 revision id ................. ............... .................. 302 c2 register definition 35.4. fpctl: c2 flash programming control ... ..................... 303 c2 register definition 35.5. fpdat: c2 flas h programming data ....... ..................... 303 rev. 1.0 17 c8051f70x/71x 1. system overview c8051f70x/71x devices are fully integrated, system- on-a-chip, capacitive se nsing mixed-signal mcus. highlighted features are listed below. refer to table 2 .1 for specific product feature selection and part ordering numbers. ?? high-speed pipelined 8051-compatible microcontroller core (up to 25 mips) ?? in-system, full-speed, non-intrus ive debug interface (on-chip) ?? capacitive sense interface with 38 input channels ?? 10-bit 500 ksps single-ended adc with 16 external channels and integrated temperature sensor ?? precision calibrated 24.5 mhz internal oscillator ?? 16 kb of on-chip flash memory ?? 512 bytes of on-chip ram ?? smbus/i 2 c, enhanced uart, and enhanced spi serial interfaces implemented in hardware ?? four general-purpose 16-bit timers ?? programmable counter/timer array (pca) with three capture/compare modules ?? on-chip internal voltage reference ?? on-chip watchdog timer ?? on-chip power-on reset and supply monitor ?? on-chip voltage comparator ?? 54 general purpose i/o with on-chip power-on reset, v dd monitor, watchdog ti mer, and clock oscillator, the c8051f70x/71x devices are truly stand-alone, system-on-a-chip so lutions. the flash memory can be reprogrammed even in-circuit, providing non-vo latile data storage, and also allowing field upgrades of th e 8051 firmware. user software has complete control of all peripherals, and ma y individually shut down any or all peripherals for power savings. the c8051f70x/71x processors incl ude silicon labora tories? 2-wire c2 debug and programming inter- face, which allows non-intrusive (uses no on-chip resources), full speed, in-circuit debugging using the pro- duction mcu installed in the final ap plication. this debug logic supports inspection of memory, viewing and modification of special function registers, setting br eakpoints, single stepping, and run and halt commands. all analog and digital peripherals are fully functional while debugging using c2. the two c2 interface pins can be shared with user functions, allowing in- system debugging without occupying package pins. each device is specified for 1.8?3.6 v operation over the industrial temperature range (?45 to +85 c). an internal ldo is used to supply the processo r core voltage at 1.8 v. the port i/o and rst pins are tolerant of input signals up to 2 v above the v dd supply, with the exception of p0.3. see table 2.1 for ordering information. block diagrams of the devices in the c8051f70x/71x family are shown in figure 1.1. c8051f70x/71x 18 rev. 1.0 figure 1.1. c8051f700/1 block diagram system clock configuration debug / programming hardware digital peripherals uart timers 0, 1, 2, 3 smbus priority crossbar decoder crossbar control port i/o configuration external clock circuit precision internal oscillator xtal2 power on reset reset sysclk xtal1 regulator core power vdd gnd peripheral power analog peripherals 10-bit 500 ksps adc a m u x temp sensor comparator + - vdd vdd vref external memory interface control address data p6 p4 / p3 p5 sfr bus pca wdt spi timer 3 / rtc port 0 drivers port 1 drivers port 2 drivers port 3 drivers port 4 drivers port 5 drivers port 6 drivers . . . . . . . . . . . . . . . p0.0 / vref p0.1 / agnd p0.2 / xtal1 p0.3 / xtal2 p0.4 p0.5 p0.6 p0.7 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p2.0 p2.7 p3.0 p3.7 p4.0 p4.7 p5.0 p5.7 p6.0 p6.5 capacitive sense (?f700 only) cip-51 8051 controller core 256 byte ram 256 byte xram 32 bytes eeprom 15 kb flash memory c2ck/rst c2d rev. 1.0 19 c8051f70x/71x figure 1.2. c8051f702/3 block diagram system clock configuration debug / programming hardware digital peripherals uart timers 0, 1, 2, 3 smbus priority crossbar decoder crossbar control port i/o configuration external clock circuit precision internal oscillator xtal2 power on reset reset sysclk xtal1 regulator core power vdd gnd peripheral power analog peripherals 10-bit 500 ksps adc a m u x temp sensor comparator + - vdd vdd vref external memory interface control address data p6 p4 / p3 p5 sfr bus pca wdt spi timer 3 / rtc port 0 drivers port 1 drivers port 2 drivers port 3 drivers port 4 drivers port 5 drivers port 6 drivers . . . . . . . . . . . . . . . p0.0 / vref p0.1 / agnd p0.2 / xtal1 p0.3 / xtal2 p0.4 p0.5 p0.6 p0.7 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p2.0 p2.7 p3.0 p3.7 p4.0 p4.7 p5.0 p5.7 p6.0 p6.5 capacitive sense (?f702 only) cip-51 8051 controller core 16 kb flash memory 256 byte ram 256 byte xram c2ck/rst c2d c8051f70x/71x 20 rev. 1.0 figure 1.3. c8051f704/5 block diagram system clock configuration debug / programming hardware digital peripherals uart timers 0, 1, 2, 4 smbus priority crossbar decoder crossbar control port i/o configuration cip-51 8051 controller core 256 byte ram external clock circuit precision internal oscillator xtal2 power on reset reset sysclk 256 byte xram xtal1 regulator core power vdd gnd peripheral power analog peripherals 10-bit 500 ksps adc a m u x temp sensor comparator + - vdd vdd vref sfr bus pca wdt spi timer 3 / rtc port 0 drivers port 1 drivers port 2 drivers port 3 drivers port 4 drivers port 5 drivers port 6 drivers 32 bytes eeprom capacitive sense 15 kb flash memory (?f704 only) . . . . . . . . . . . . . . . p0.0 / vref p0.1 / agnd p0.2 / xtal1 p0.3 / xtal2 p0.4 p0.5 p0.6 p0.7 p1.0 p1.1 p1.2 p1.3 p2.0 p2.7 p3.0 p3.7 p4.0 p4.3 p5.0 p5.7 p6.0 p6.5 (8 i/o) (8 i/o) (8 i/o) (4 i/o) (6 i/o) c2ck/rst c2d rev. 1.0 21 c8051f70x/71x figure 1.4. c8051f706/07 block diagram system clock configuration debug / programming hardware digital peripherals uart timers 0, 1, 2, 4 smbus priority crossbar decoder crossbar control port i/o configuration cip-51 8051 controller core 16 kb flash memory 256 byte ram external clock circuit precision internal oscillator xtal2 power on reset reset sysclk 256 byte xram xtal1 regulator core power vdd gnd peripheral power analog peripherals 10-bit 500 ksps adc a m u x temp sensor comparator + - vdd vdd vref sfr bus pca wdt spi timer 3 / rtc port 0 drivers port 1 drivers port 2 drivers port 3 drivers port 4 drivers port 5 drivers port 6 drivers . . . . . . . . . . . . . . . p0.0 / vref p0.1 / agnd p0.2 / xtal1 p0.3 / xtal2 p0.4 p0.5 p0.6 p0.7 p1.0 p1.1 p1.2 p1.3 p2.0 p2.7 p3.4 p3.7 p4.0 p4.3 p5.0 p5.7 p6.3 p6.5 capacitive sense (?f706 only) (8 i/o) (4 i/o) (8 i/o) (4 i/o) (3 i/o) c2ck/rst c2d c8051f70x/71x 22 rev. 1.0 figure 1.5. c8051f708/09/10/11 block diagram system clock configuration debug / programming hardware digital peripherals uart timers 0, 1, 2, 3 smbus priority crossbar decoder crossbar control port i/o configuration external clock circuit precision internal oscillator xtal2 power on reset reset sysclk xtal1 regulator core power vdd gnd peripheral power analog peripherals 10-bit 500 ksps adc a m u x temp sensor comparator + - vdd vdd vref external memory interface control address data p6 p4 / p3 p5 sfr bus pca wdt spi timer 3 / rtc port 0 drivers port 1 drivers port 2 drivers port 3 drivers port 4 drivers port 5 drivers port 6 drivers . . . . . . . . . . . . . . . p0.0 / vref p0.1 / agnd p0.2 / xtal1 p0.3 / xtal2 p0.4 p0.5 p0.6 p0.7 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p2.0 p2.7 p3.0 p3.7 p4.0 p4.7 p5.0 p5.7 p6.0 p6.5 capacitive sense cip-51 8051 controller core 256 byte ram 256 byte xram 8 kb flash memory (?f708/10 only) 32 bytes eeprom (?f708/09 only) c2ck/rst c2d rev. 1.0 23 c8051f70x/71x figure 1.6. c8051f712/13/14/15 block diagram system clock configuration debug / programming hardware digital peripherals uart timers 0, 1, 2, 4 smbus priority crossbar decoder crossbar control port i/o configuration cip-51 8051 controller core 8 kb flash memory 256 byte ram external clock circuit precision internal oscillator xtal2 power on reset reset sysclk 256 byte xram xtal1 regulator core power vdd gnd peripheral power analog peripherals 10-bit 500 ksps adc a m u x temp sensor comparator + - vdd vdd vref sfr bus pca wdt spi timer 3 / rtc port 0 drivers port 1 drivers port 2 drivers port 3 drivers port 4 drivers port 5 drivers port 6 drivers . . . . . . . . . . . . . . . p0.0 / vref p0.1 / agnd p0.2 / xtal1 p0.3 / xtal2 p0.4 p0.5 p0.6 p0.7 p1.0 p1.1 p1.2 p1.3 p2.0 p2.7 p3.4 p3.7 p4.0 p4.3 p5.0 p5.7 p6.3 p6.5 capacitive sense (8 i/o) (4 i/o) (8 i/o) (4 i/o) (3 i/o) 32 bytes eeprom (?f712/13 only) (?f712/14 only) c2ck/rst c2d c8051f70x/71x 24 rev. 1.0 figure 1.7. c8051f716 block diagram system clock configuration debug / programming hardware digital peripherals uart timers 0, 1, 2, 4 smbus priority crossbar decoder crossbar control port i/o configuration cip-51 8051 controller core 16 kb flash memory 256 byte ram external clock circuit precision internal oscillator xtal2 power on reset reset sysclk 256 byte xram xtal1 regulator core power vdd gnd peripheral power analog peripherals 10-bit 500 ksps adc a m u x temp sensor comparator + - vdd vdd vref sfr bus pca wdt spi timer 3 / rtc port 0 drivers port 2 drivers port 3 drivers port 5 drivers port 6 drivers . . . . . . . . . p0.3 / xtal2 p0.4 p0.5 p2.0 p2.7 p3.0 p3.6 p5.0 p5.7 p6.3 p6.5 capacitive sense (8 i/o) (7 i/o) (8 i/o) p6.4 c2ck/rst c2d rev. 1.0 25 c8051f70x/71x figure 1.8. c8051f717 block diagram system clock configuration debug / programming hardware digital peripherals uart timers 0, 1, 2, 4 smbus priority crossbar decoder crossbar control port i/o configuration cip-51 8051 controller core 16 kb flash memory 256 byte ram external clock circuit precision internal oscillator xtal2 power on reset reset sysclk 256 byte xram xtal1 regulator core power vdd gnd peripheral power analog peripherals comparator + - sfr bus pca wdt spi timer 3 / rtc port 0 drivers port 2 drivers port 4 drivers port 6 drivers . . . . . . p0.4 p0.5 p2.0 p2.7 p4.0 p4.7 p6.4 p6.5 capacitive sense (8 i/o) (8 i/o) c2ck/rst c2d c8051f70x/71x 26 rev. 1.0 2. ordering information all c8051f70x/71x devices have the following features: ? 25 mips (peak) ? calibrated internal oscillator ? smbus/i 2 c ? uart ? programmable counter array (3 channels) ? 4 timers (16-bit) ? 1 comparator ? pb-free (rohs compliant) package ? 512 bytes ram in addition to the features listed abov e, each device in the c8051f70x/71x family has a set of features that vary across the product line. see table 2.1 for a complete list of the unique feature sets for each device in the family. rev. 1.0 27 c8051f70x/71x table 2.1. product selection guide part number digital port i/os capacitive sense channels flash memory (kb) eeprom (bytes) external memory interface 10-bit 500 ksps adc adc channels temperature sensor package (rohs) c8051f700-gq 54 38 15 32 y y 16 y tqfp-64 c8051f701-gq 54 38 15 32 y n ? ?tqfp-64 c8051f702-gq 54 38 16 ? y y 16 y tqfp-64 c8051f703-gq 54 38 16 ? y n ? ?tqfp-64 c8051f704-gq 39 27 15 32 n y 12 y tqfp-48 c8051f704-gm 39 27 15 32 n y 12 y qfn-48 c8051f705-gq 39 27 15 32 n n ? ? tqfp-48 c8051f705-gm 39 27 15 32 n n ? ? qfn-48 c8051f706-gq 39 27 16 ? ny12y tqfp-48 c8051f706-gm 39 27 16 ? ny12y qfn-48 c8051f707-gq 39 27 16 ? n n ? ? tqfp-48 c8051f707-gm 39 27 16 ? n n ? ? qfn-48 c8051f708-gq 54 38 8 32 y y 16 y tqfp-64 c8051f709-gq 54 38 832y n ? ?tqfp-64 c8051f710-gq 54 38 8 ? y y 16 y tqfp-64 c8051f711-gq 54 38 8 ? y n ? ?tqfp-64 c8051f712-gq 39 27 832ny12y tqfp-48 c8051f712-gm 39 27 832ny12y qfn-48 c8051f713-gq 39 27 832n n ? ? tqfp-48 c8051f713-gm 39 27 832n n ? ? qfn-48 c8051f714-gq 39 27 8 ? ny12y tqfp-48 C8051F714-GM 39 27 8 ? ny12y qfn-48 c8051f715-gq 39 27 8 ? n n ? ? tqfp-48 c8051f715-gm 39 27 8 ? n n ? ? qfn-48 c8051f716-gm 29 26 16 ? ny3yqfn-32 c8051f717-gm 20 18 16 ? n n ? ? qfn-24 lead finish material on all devices is 100% matte tin (sn). c8051f70x/71x 28 rev. 1.0 3. pin definitions table 3.1. pin definitions for the c8051f70x/71x name tqfp64 tqfp48 qfn48 qfn32 qfn24 type description v dd 8, 24, 41, 57 8, 20, 44 27 21 power supply voltage. gnd 9, 25, 40, 56 9, 21, 30, 43 center 20 ground. rst / c2ck 58 45 28 22 d i/o d i/o device reset. open-drain output of internal por or v dd monitor. clock signal for the c2 debug interface. c2d 59 46 29 23 d i/o bi-directional data signal for the c2 debug interface. p0.0 / vref 55 42 ? ? d i/o or a in a in port 0.0. adc0 input. external vref input. p0.1/ agnd 54 41 ? ? d i/o or a in port 0.1. adc0 input. external agnd input. p0.2 / xtal1 53 40 ? ? d i/o or a in a in port 0.2. adc0 input. external clock pin. this pin can be used for crystal clock mode. p0.3 / xtal2 52 39 26 ? d i/o or a in a i/o or d in port 0.3. adc0 input. external clock pin. this pin can be used for rc, crystal, and cmos clock modes. p0.4 51 38 25 19 d i/o or a in port 0.4. adc0 input. p0.5 50 37 24 18 d i/o or a in port 0.5. adc0 input. p0.6 49 36 ? ? d i/o or a in port 0.6. adc0 input. rev. 1.0 29 c8051f70x/71x p0.7 48 35 ? ? d i/o or a in port 0.7. adc0 input. p1.0 47 34 ? ? d i/o or a in port 1.0. adc0 input. p1.1 46 33 ? ? d i/o or a in port 1.1. adc0 input. p1.2 45 32 ? ? d i/o or a in port 1.2. adc0 input. p1.3 44 31 ? ? d i/o or a in port 1.3. adc0 input. p1.4 43 ? ? ? d i/o or a in port 1.4. adc0 input. p1.5 42 ? ? ? d i/o or a in port 1.5. adc0 input. p1.6 39 ? ? ? d i/o or a in port 1.6. adc0 input. p1.7 38 ? ? ? d i/o or a in port 1.7. adc0 input. p2.0 37 29 23 17 d i/o or a in port 2.0. cs0 input pin 1. p2.1 36 28 22 16 d i/o or a in port 2.1. cs0 input pin 2. p2.2 35 27 21 15 d i/o or a in port 2.2. cs0 input pin 3. p2.3 34 26 20 14 d i/o or a in port 2.3. cs0 input pin 4. p2.4 33 25 19 13 d i/o or a in port 2.4. cs0 input pin 5. p2.5 32 24 18 12 d i/o or a in port 2.5. cs0 input pin 6. p2.6 31 23 17 11 d i/o or a in port 2.6. cs0 input pin 7. p2.7 30 22 16 10 d i/o or a in port 2.7. cs0 input pin 8. table 3.1. pin definitions for the c8051f70x/71x (continued) name tqfp64 tqfp48 qfn48 qfn32 qfn24 type description c8051f70x/71x 30 rev. 1.0 p3.0 29 ? 15 ? d i/o or a in port 3.0. cs0 input pin 9. p3.1 28 ? 14 ? d i/o or a in port 3.1. cs0 input pin 10. p3.2 27 ? 13 ? d i/o or a in port 3.2. cs0 input pin 11. p3.3 26 ? 12 ? d i/o or a in port 3.3. cs0 input pin 12. p3.4 23 19 11 ? d i/o or a in port 3.4. cs0 input pin 13. p3.5 22 18 10 ? d i/o or a in port 3.5. cs0 input pin 14. p3.6 21 17 9 ? d i/o or a in port 3.6. cs0 input pin 15. p3.7 20 16 ? ? d i/o or a in port 3.7. cs0 input pin 16. p4.0 19 15 ? 9 d i/o or a in port 4.0. cs0 input pin 17. p4.1 18 14 ? 8 d i/o or a in port 4.1. cs0 input pin 18. p4.2 17 13 ? 7 d i/o or a in port 4.2. cs0 input pin 19. p4.3 16 12 ? 6 d i/o or a in port 4.3. cs0 input pin 20. p4.4 15 ? ? 5 d i/o or a in port 4.4. cs0 input pin 21. p4.5 14 ? ? 4 d i/o or a in port 4.5. cs0 input pin 22. p4.6 13 ? ? 3 d i/o or a in port 4.6. cs0 input pin 23. p4.7 12 ? ? 2 d i/o or a in port 4.7. cs0 input pin 24. p5.0 11 11 8 - d i/o or a in port 5.0. cs0 input pin 25. table 3.1. pin definitions for the c8051f70x/71x (continued) name tqfp64 tqfp48 qfn48 qfn32 qfn24 type description rev. 1.0 31 c8051f70x/71x p5.1 10 10 7 ? d i/o or a in port 5.0. cs0 input pin 26. p5.2 7 7 6 ? d i/o or a in port 5.2. cs0 input pin 27 p5.3 6 6 5 ? d i/o or a in port 5.3. cs0 input pin 28. p5.4 5 5 4 ? d i/o or a in port 5.4. cs0 input pin 29. p5.5 4 4 3 ? d i/o or a in port 5.5. cs0 input pin 30. p5.6 3 3 2 ? d i/o or a in port 5.6. cs0 input pin 31. p5.7 2 2 1 ? d i/o or a in port 5.7. cs0 input pin 32. p6.0 1 ? ? ? d i/o port 6.0. cs0 input pin 33. p6.1 64 ? ? ? d i/o port 6.1. cs0 input pin 34. p6.2 63 ? ? ? d i/o port 6.2. cs0 input pin 35. p6.3 62 1 32 ? d i/o port 6.3. cs0 input pin 36. p6.4 61 48 31 1 d i/o port 6.4. cs0 input pin 37. p6.5 60 47 30 24 d i/o port 6.5. cs0 input pin 38. table 3.1. pin definitions for the c8051f70x/71x (continued) name tqfp64 tqfp48 qfn48 qfn32 qfn24 type description c8051f70x/71x 32 rev. 1.0 figure 3.1. c8051f7xx-gq tqfp64 pinout diagram (top view) c8051f700/01/02/03/08/09/10/11 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 p6.1 p6.2 p6.3 p6.4 p6.5 c2d rst/c2ck vdd gnd p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 vdd gnd p1.6 p1.7 p2.0 p2.1 p2.2 p2.3 p2.4 p6.0 p5.7 p5.6 p5.5 p5.4 p5.3 p5.2 vdd gnd p5.1 p5.0 p4.7 p4.6 p4.5 p4.4 p4.3 p4.2 p4.1 p4.0 p3.7 p3.6 p3.5 p3.4 vdd gnd p3.3 p3.2 p3.1 p3.0 p2.7 p2.6 p2.5 rev. 1.0 33 c8051f70x/71x figure 3.2. c8051f7xx-gq qfp48 pinout diagram (top view) 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37 p4.3 p0.6 p0.4 p0.3 p0.2 vdd p1.0 p0.7 p2.4 p2.3 p2.1 p2.0 p0.5 p6.4 p2.2 p6.5 p5.5 gnd p5.0 p5.6 gnd p0.0 p0.1 p6.3 rst/c2ck c2d p5.7 gnd 13 14 15 16 17 18 19 20 21 22 23 24 p1.2 p1.1 c8051f704/05/06/07/ 12/13/14/15 p5.2 vdd p5.4 p5.3 p5.1 p1.3 p2.5 gnd p2.7 p2.6 vdd p3.6 p3.5 p3.4 p3.7 p4.2 p4.1 p4.0 c8051f70x/71x 34 rev. 1.0 figure 3.3. c8051f7xx-gm qfn48 pinout diagram (top view) p4.3 p0.6 p0.4 p0.3 p0.2 vdd p1.0 p0.7 p2.4 p2.3 p2.1 p2.0 p0.5 p6.4 p2.2 p6.5 p5.5 gnd p5.0 p5.6 gnd p0.0 p0.1 p6.3 rst/c2ck c2d p5.7 gnd p1.2 p1.1 c8051f704/05/06/07/ 12/13/14/15 p5.2 vdd p5.4 p5.3 p5.1 p1.3 p2.5 gnd p2.7 p2.6 vdd p3.6 p3.5 p3.4 p3.7 p4.2 p4.1 p4.0 gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 rev. 1.0 35 c8051f70x/71x figure 3.4. c8051f716-gm qfn32 pinout diagram (top view) 3 4 5 1 2 23 22 21 24 31 32 29 30 c8051f716 6 20 19 27 28 1 0 1 1 1 2 9 1 3 1 4 p 6 . 5 p 6 . 3 p 6 . 4 p2.1 p0.5 p2.0 p2.2 p2.3 p2.4 p 3 . 4 p 3 . 6 p 3 . 5 p 3 . 3 p 3 . 2 p 3 . 1 p5.5 p5.7 p5.6 p5.4 p5.3 p5.2 2 5 2 6 p 0 . 3 p 0 . 4 1 5 1 6 p 3 . 0 p 2 . 7 18 17 p2.5 p2.6 7 8 p5.1 p5.0 r s t / c 2 c k c 2 d v d d gnd c8051f70x/71x 36 rev. 1.0 figure 3.5. c8051f717-gm qfn24 pinout diagram (top view) 3 4 5 1 2 17 16 15 18 23 24 21 22 c8051f717 6 14 13 19 20 8 9 1 0 7 1 1 1 2 r s t / c 2 c k p 6 . 5 c 2 d v d d g n d p 0 . 4 p2.1 p0.5 p2.0 p2.2 p2.3 p2.4 p 4 . 0 p 4 . 2 p 4 . 1 p 2 . 7 p 2 . 6 p 2 . 5 p4.6 p6.4 p4.7 p4.5 p4.4 p4.3 gnd rev. 1.0 37 c8051f70x/71x 4. tqfp-64 package specifications figure 4.1. tqfp-64 package drawing table 4.1. tqfp-64 package dimensions dimension min nom max dimension min nom max a ? ? 1.20 e 12.00 bsc. a1 0.05 ? 0.15 e1 10.00 bsc. a2 0.95 1.00 1.05 l 0.45 0.60 0.75 b 0.17 0.22 0.27 aaa ? ? 0.20 c 0.09 ? 0.20 bbb ? ? 0.20 d 12.00 bsc. ccc ? ? 0.08 d1 10.00 bsc. ddd ? ? 0.08 e 0.50 bsc. 0 ? 3.5 ? 7 ? notes: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this package outline conforms to jedec ms-026, variant acd. 4. recommended card reflow profile is per the jede c/ipc j-std-020 specific ation for small body components. c8051f70x/71x 38 rev. 1.0 figure 4.2. tqfp-64 pcb land pattern table 4.2. tqfp-64 pcb land pattern dimensions dimension min max c1 11.30 11.40 c2 11.30 11.40 e 0.50 bsc x0 . 2 00 . 3 0 y1 . 4 01 . 5 0 notes: general 1. all dimensions shown are in mill imeters (mm) unless otherwise noted. 2. this land pattern design is based on the ipc-7351 guidelines. solder mask design 3. all metal pads are to be non-solder mask defined (nsmd) . clearance between the solder mask and the metal pad is to be 60 ? m minimum, all the way around the pad. stencil design 4. a stainless steel, laser-cut and electro-polished stenc il with trapezoidal walls should be used to assure good solder paste release. 5. the stencil thickness should be 0.125 mm (5 mils). 6. the ratio of stencil aperture to land pa d size should be 1:1 for all perimeter pins. card assembly 7. a no-clean, type-3 solder paste is recommended. 8. the recommended card reflow profile is per the je dec/ipc j-std-020 specification for small body components. rev. 1.0 39 c8051f70x/71x 5. tqfp-48 package specifications figure 5.1. tqfp-48 package drawing table 5.1. tqfp-48 package dimensions dimension min nom max dimension min nom max a ? ? 1.20 e 9.00 bsc. a1 0.05 ? 0.15 e1 7.00 bsc. a2 0.95 1.00 1.05 l 0.45 0.60 0.75 b 0.17 0.22 0.27 aaa 0.20 c 0.09 ? 0.20 bbb 0.20 d 9.00 bsc. ccc 0.08 d1 7.00 bsc. ddd 0.08 e 0.50 bsc. 0 3.5 7 notes: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to jedec outline ms-026, variation abc. 4. recommended card reflow profile is per the jede c/ipc j-std-020 specific ation for small body components. ? c8051f70x/71x 40 rev. 1.0 figure 5.2. tqfp-48 pcb land pattern table 5.2. tqfp-48 pcb land pattern dimensions dimension min max c1 8.30 8.40 c2 8.30 8.40 e 0.50 bsc x1 0.20 0.30 y1 1.40 1.50 notes: general 1. all dimensions shown are in mill imeters (mm) unless otherwise noted. 2. this land pattern design is based on the ipc-7351 guidelines. solder mask design 3. all metal pads are to be non-solder mask defined (nsmd) . clearance between the solder mask and the metal pad is to be 60 ? m minimum, all the way around the pad. stencil design 4. a stainless steel, laser-cut and electro-polished stenc il with trapezoidal walls should be used to assure good solder paste release. 5. the stencil thickness should be 0.125 mm (5 mils). 6. the ratio of stencil aperture to land pad size should be 1:1 for all pads. card assembly 7. a no-clean, type-3 solder paste is recommended. 8. the recommended card reflow profile is per the je dec/ipc j-std-020 specification for small body components. rev. 1.0 41 c8051f70x/71x 6. qfn-48 package specifications figure 6.1. qfn-48 package drawing table 6.1. qfn-48 package dimensions dimension min nom max dimension min nom max a 0.80 0.90 1.00 e2 3.90 4.00 4.10 a1 0.00 ? 0.05 l 0.30 0.40 0.50 b 0.18 0.23 0.30 l1 0.00 ? 0.10 d 7.00 bsc. aaa ? ? 0.10 d2 3.90 4.00 4.10 bbb ? ? 0.10 e 0.50 bsc. ccc ? ? 0.05 e 7.00 bsc. ddd ? ? 0.08 notes: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. 3.this drawing conforms to jede c outline mo-220, vari ation vkkd-4 except for features d2 and l which are toleranced per supplier designation. 4. recommended card reflow profile is per the jede c/ipc j-std-020 specific ation for small body components. ? c8051f70x/71x 42 rev. 1.0 figure 6.2. qfn-48 pcb land pattern table 6.2. qfn-48 pcb land pattern dimensions dimension min max e 0.50 bsc c1 6.80 6.90 c2 6.80 6.90 x1 0.20 0.30 x2 4.00 4.10 y1 0.75 0.85 y2 4.00 4.10 notes: general 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing is per the ansi y14.5m-1994 specification. 3. this land pattern design is based on ipc-sm-7351 guidelines. 4. all dimensions shown are at maximum material condition (mmc). least material condition (lmc) is calculated based on a fabrication allowance of 0.05 mm. solder mask design 5. all metal pads are to be non-solder mask defined (nsmd) . clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 6. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 7. the stencil thickness should be 0.125 mm (5 mils). 8. the ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 9. a 3x3 array of 1.20 mm square openings on 1.40 mm pitch should be used for the center ground pad. card assembly 10. a no-clean, type-3 solder paste is recommended. 11. the recommended card reflow profile is per the jedec/ ipc j-std-020 specification for small body components. ? rev. 1.0 43 c8051f70x/71x 7. qfn-32 package specifications figure 7.1. qfn-32 package drawing table 7.1. qfn-32 package dimensions dimension min typ max dimension min typ max a 0.80 0.90 1.00 e2 3.50 3.60 3.70 a1 0.00 0.02 0.05 l 0.30 0.35 0.40 b 0.18 0.25 0.30 l1 0.00 ? 0.10 d 5.00 bsc. aaa 0.15 d2 3.50 3.60 3.70 bbb 0.10 e 0.50 bsc. ddd 0.05 e 5.00 bsc. eee 0.08 notes: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec solid state outline mo-220, variation vhhd except for custom features d2, e2, l and l1 which are toleranced per supplier designation. 4. recommended card reflow profile is per the jede c/ipc j-std-020 specific ation for small body components. c8051f70x/71x 44 rev. 1.0 figure 7.2. qfn-32 recommended pcb land pattern table 7.2. qfn-32 pcb land pattern dimensions dimension min max dimension min max c1 4.60 x2 3.60 3.70 c2 4.60 y1 0.45 0.55 e 0.50 y2 3.60 3.70 x1 0.20 0.30 notes: general 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing is per the ansi y14.5m-1994 specification. 3. this land pattern design is based on the ipc-7351 guidelines. solder mask design 4. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 5. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 6. the stencil thickness should be 0.125 mm (5 mils). 7. the ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins. 8. a 3x3 array of 1.0 mm openings on a 1.25 mm pitch should be used for the center pad to assure the proper paste volume. card assembly 9. a no-clean, type-3 solder paste is recommended. 10. the recommended card reflow profile is per th e jedec/ipc j-std-020 specification for small body components. rev. 1.0 45 c8051f70x/71x 8. qfn-24 package specifications figure 8.1. qfn-24 package drawing table 8.1. qfn-24 package dimensions dimension min typ max dimension min typ max a 0.70 0.75 0.80 l 0.30 0.40 0.50 a1 0.00 0.02 0.05 l1 0.00 ? 0.15 b 0.18 0.25 0.30 aaa ? ? 0.15 d 4.00 bsc. bbb ? ? 0.10 d2 2.55 2.70 2.80 ddd ? ? 0.05 e 0.50 bsc. eee ? ? 0.08 e 4.00 bsc. z ? 0.24 ? e2 2.55 2.70 2.80 y ? 0.18 ? notes: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to jedec solid state outline mo-220, variation wggd except for custom features d2, e2, z, y, and l wh ich are toleranced per supplier designation. 4. recommended card reflow profile is per the jede c/ipc j-std-020 specific ation for small body components. c8051f70x/71x 46 rev. 1.0 figure 8.2. qfn-24 recommended pcb land pattern table 8.2. qfn-24 pcb land pattern dimensions dimension min max dimension min max c1 3.90 4.00 x2 2.70 2.80 c2 3.90 4.00 y1 0.65 0.75 e 0.50 bsc y2 2.70 2.80 x1 0.20 0.30 notes: general 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. this land pattern design is based on the ipc-7351 guidelines. solder mask design 3. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 4. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 5. the stencil thickness should be 0.125 mm (5 mils). 6. the ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 7. a 2x2 array of 1.10 mm x 1.10 mm openings on a 1.30 mm pitch should be used for the center pad. card assembly 8. a no-clean, type-3 solder paste is recommended. 9. the recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. ? rev. 1.0 47 c8051f70x/71x 9. electrical characteristics 9.1. absolute m aximum specifications table 9.1. absolute maximum ratings parameter conditions min typ max units ambient temperature under bias ?55 ? 125 c storage temperature ?65 ? 150 c voltage on rst or any port i/o pin (except p0.3) with respect to gnd ?0.3 ? v dd +2.0 v voltage on p0.3 with respect to gnd ?0.3 ? v dd +0.3 v voltage on v dd with respect to gnd regulator in normal mode regulator in bypass mode ?0.3 ?0.3 ? ? 4.2 1.98 v v maximum total current through v dd and gnd ??500ma maximum output current sunk by rst or any port pin ??100ma note: stresses above those listed under ?absolute maximum ra tings? may cause permanent damage to the device. this is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation list ings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. c8051f70x/71x 48 rev. 1.0 9.2. electrical characteristics table 9.2. global electrical characteristics ?40 to +85 c, 25 mhz system clock unless otherwise specified. parameter conditions min typ max units supply voltage 1 regulator in normal mode regulator in bypass mode 1.8 1.7 3.0 1.8 3.6 1.9 v v digital supply current with cpu active (normal mode 2,3 ) v dd = 1.8 v, clock = 25 mhz v dd = 1.8 v, clock = 1 mhz v dd = 1.8 v, clock = 32 khz v dd = 3.0 v, clock = 25 mhz v dd = 3.0 v, clock = 1 mhz v dd = 3.0 v, clock = 32 khz ? ? ? ? ? ? 5.0 1.2 175 5.5 1.3 190 6.5 ? ? 7.0 ? ? ma ma a ma ma a digital supply current with cpu inactive (idle mode 2,3 ) v dd = 1.8 v, clock = 25 mhz v dd = 1.8 v, clock = 1 mhz v dd = 1.8 v, clock = 32 khz v dd = 3.0 v, clock = 25 mhz v dd = 3.0 v, clock = 1 mhz v dd = 3.0 v, clock = 32 khz ? ? ? ? ? ? 2.5 180 90 3.2 200 110 4.0 ? ? 4.5 ? ? ma a a ma a a digital supply current (shutdown) 3 stop/suspend mode, reg on, 25 c ? 80 90 a stop/suspend mode, reg bypass, 25 c ? 2 4 a digital supply ram data retention voltage ?1.3? v specified operating temperature range ?40 ? +85 c sysclk (system clock frequency) see note 3. 0 ? 25 mhz tsysl (sysclk low time) 18 ? ? ns tsysh (sysclk high time) 18 ? ? ns notes: 1. analog performance is not guaranteed when v dd is below 1.8 v. 2. includes bias current for internal voltage regulator. 3. sysclk must be at least 32 khz to enable debugging. rev. 1.0 49 c8051f70x/71x table 9.3. port i/o dc electrical characteristics v dd = 1.8 to 3.6 v, ?40 to +85 c unless otherwise specified. parameters conditions min typ max units output high voltage high drive strength i oh = ?3 ma, port i/o push-pull i oh = ?10 a, port i/o push-pull i oh = ?10 ma, port i/o push-pull low drive strength i oh = ?1 ma, port i/o push-pull i oh = ?10 a, port i/o push-pull i oh = ?3 ma, port i/o push-pull v dd ?0.7 v dd ?0.1 ? v dd ?0.7 v dd ?0.1 ? ? ? v dd ?0.8 ? ? v dd ?0.8 ? ? ? ? ? ? v v v v v v output low voltage high drive strength i ol = 8.5 ma i ol = 10 a i ol = 25 ma low drive strength i ol = 1.4 ma i ol = 10 a i ol = 4 ma ? ? ? ? ? ? ? ? 1.0 ? ? 1.0 0.6 0.1 ? 0.6 0.1 ? v v v v v v input high voltage 0.75 x v dd ??v input low voltage ? ? 0.6 v input leakage current weak pullup off weak pullup on, v in = 0 v ?1 ? ? 25 1 50 a a table 9.4. reset electrical characteristics v dd = 1.8 to 3.6 v, ?40 to +85 c unless otherwise specified. parameter conditions min typ max units rst output low voltage i ol = 8.5 ma, v dd = 1.8 v to 3.6 v ??0.6v rst input high voltage 0.75 x v dd ?? v rst input low voltage ? ? 0.3 x v dd v dd rst input pullup current rst = 0.0 v ? 25 50 a v dd por ramp time ? ? 1 ms v dd monitor threshold (v rst ) 1.7 1.75 1.8 v missing clock detector timeout time from last system clock rising edge to reset initiation 100 500 1000 s reset time delay delay between release of any reset source and code execution at location 0x0000 ??30s minimum rst low time to generate a system reset 15 ? ? s v dd monitor turn-on time v dd = v rst ? 0.1 v ? 50 ? s v dd monitor supply current ? 25 30 a c8051f70x/71x 50 rev. 1.0 table 9.5. internal voltage regulator electrical characteristics v dd = 3.0 v, ?40 to +85 c unless otherwise specified. parameter conditions min typ max units input voltage range 1.8 ? 3.6 v bias current normal mode, 25 c ? 80 90 a bypass mode, 25 c ? 2 4 a table 9.6. flash electrical characteristics parameter conditions min typ max units flash size* c8051f702/3/6/7, c8051f716/7 c8051f700/1/4/5 c8051f708/9, c805 1f710/1/2/3/4/5 16384 15360 8192 bytes bytes bytes endurance (erase/write) 10000 ? ? cycles erase cycle time 25 mhz clock 15 20 26 ms write cycle time 25 mhz clock 15 20 26 s clock speed during flash write/erase operations 1??mhz *note: includes security lock byte. table 9.7. internal high-frequency oscillator electrical characteristics v dd = 1.8 to 3.6 v; t a = ?40 to +85 c unless otherwise specif ied. use factory-calibrated settings. parameter conditions min typ max units oscillator frequency ifcn = 11b 24 24.5 25 mhz oscillator supply current 25 c, v dd = 3.0 v, oscicn.7 = 1, ocsicn.5 = 0 ? 350 650 a rev. 1.0 51 c8051f70x/71x table 9.8. capacitive sense electrical characteristics v dd = 1.8 to 3.6 v; t a = ?40 to +85 c unless otherwise specified. parameter conditions min typ max units single conversion time 1 12-bit mode 13-bit mode (default) 14-bit mode 16-bit mode 20 21 23 26 29 31 33 38 40 42.5 45 50 s number of channe ls 64-pin packages 48-pin packages 32-pin packages 24-pin packages 38 27 26 18 channels capacitance per code default configuration ? 1 ? ff external capacitive load cs0cg = 111b (default) cs0cg = 000b ? ? ? ? 45 500 pf pf external series impedance cs0cg = 111b (default) ? ? 50 k ? quantization noise 12 rms peak-to-peak ? ? 3 20 ? ? ff ff power supply current cs module bias current, 25 c ? 50 60 a cs module alone, maximum code output, 25 c ? 90 105 a wake-on-cs threshold (suspend mode with regulator and cs module on) 3 ? 130 145 a notes: 1. conversion time is specified with the default configuration. 2. rms noise is equivalent to one standard deviation. peak-to-peak noise encompasses 3.3 standard deviations. the rms noise value is spec ified with the default configuration. 3. includes only current from regulator, cs module, and mcu in suspend mode. c8051f70x/71x 52 rev. 1.0 table 9.9. eeprom electrical characteristics v dd = 1.8 to 3.6 v; t a = ?40 to +85 c unless otherwise specif ied. use factory-calibrated settings. parameter conditions min typ max units write to eeprom from ram ? 3 ms read of eeprom to ram ? 50 x t sysclk ?s endurance (writes) 300000 ? ? cycles clock speed during eeprom write operations 1??mhz note: t sysclk is equal to one per iod of the device system clock (sysclk). table 9.10. adc0 electrical characteristics v dd = 3.0 v, vref = 2.40 v (refsl=0), ? 40 to +85 c unless otherwise specified. parameter conditions min typ max units dc accuracy resolution 10 bits integral nonlinearity ? 0.5 1 lsb differential nonlinearity guar anteed monotonic ? 0.5 1 lsb offset error ?2 0 2 lsb full scale error ?2 0 2 lsb offset temperature coefficient ? 45 ? ppm/c dynamic performance (10 khz sine-wave single- ended input, 1 db below full scale, 500 ksps) signal-to-noise plus distortion 56 60 ? db total harmonic distortion up to the 5th harmonic ? 72 ? db spurious-free dynamic range ? ?75 ? db conversion rate sar conversion clock ? ? 8.33 mhz conversion time in sar clocks 10-bit mode 8-bit mode 13 11 ? ? ? ? clocks clocks track/hold acquisition time v dd >= 2.0 v v dd < 2.0 v 300 2.0 ? ? ? ? ns s throughput rate ? ? 500 ksps analog inputs adc input voltage range 0 ? vref v sampling capacitance 1x gain 0.5x gain ? ? 5 3 ? ? pf pf input multiplexer impedance ? 5 ? k ? power specifications power supply current operating mode, 500 ksps ? 600 1000 a power supply rejection ? ?70 ? db rev. 1.0 53 c8051f70x/71x table 9.11. power management electrical characteristics v dd = 1.8 to 3.6 v; t a = ?40 to +85 c unless otherwise specif ied. use factory-calibrated settings. parameter conditions min typ max units idle mode wake-u p time 2 ? 3 sysclks suspend mode wake-up time ? 250 ? ns table 9.12. temperature sensor electrical characteristics v dd = 3.0 v, ? 40 to +85 c unless otherwise specified. parameter conditions min typ max units linearity ? 1 ? c slope ? 3.27 ? mv/c slope error* ? 65 ? v/c offset temp = 0 c ? 868 ? mv offset error* temp = 0 c ? 15.3 ? mv *note: represents one standard deviation from the mean. table 9.13. voltage reference electrical characteristics v dd = 1.8 to 3.6 v; ?40 to +85 c unless otherwise specified. parameter conditions min typ max units internal high-speed reference (refsl[1:0] = 11) output voltage 25 c ambient 1.55 1.59 1.70 v turn-on time ? ? 1.7 s supply current ? 200 ? a external reference (ref0e = 0) input voltage range 0 ? v dd input current sample rate = 500 ksps; vref = 3.0 v ? 7 ? a c8051f70x/71x 54 rev. 1.0 table 9.14. comparator electrical characteristics v dd = 3.0 v, ?40 to +85 c unless otherwise noted. parameter conditions min typ max units response time: mode 0, vcm * = 1.5 v cp0+ ? cp0? = 100 mv ? 300 ? ns cp0+ ? cp0? = ?100 mv ? 200 ? ns response time: mode 1, vcm * = 1.5 v cp0+ ? cp0? = 100 mv ? 400 ? ns cp0+ ? cp0? = ?100 mv ? 350 ? ns response time: mode 2, vcm * = 1.5 v cp0+ ? cp0? = 100 mv ? 570 ? ns cp0+ ? cp0? = ?100 mv ? 870 ? ns response time: mode 3, vcm * = 1.5 v cp0+ ? cp0? = 100 mv ? 1500 ? ns cp0+ ? cp0? = ?100 mv ? 4500 ? ns common-mode rejection ratio ? 1 4 mv/v positive hysteresis 1 mod e 2, cp0hyp1?0 = 00 ? 0 1 mv positive hysteresis 2 mod e 2, cp0hyp1?0 = 01 2 5 10 mv positive hysteresis 3 mode 2, cp0hyp1?0 = 10 7 10 20 mv positive hysteresis 4 mode 2, cp0hyp1?0 = 11 10 20 30 mv negative hysteresis 1 mode 2, cp0hyn1?0 = 00 ? 0 1 mv negative hysteresis 2 mode 2, cp0hyn1?0 = 01 2 5 10 mv negative hysteresis 3 mode 2, cp0hyn1?0 = 10 7 10 20 mv negative hysteresis 4 mode 2, cp0hyn1?0 = 11 10 20 30 mv inverting or non- inverting input voltage range ?0.25 ? v dd + 0.25 v input offset voltage ?7.5 ? 7.5 mv power specifications power supply rejection ? 0.1 ? mv/v powerup time ? 10 ? s supply current at dc mode 0 ? 25 ? a mode 1 ? 10 ? a mode 2 ? 3 ? a mode 3 ? 0.5 ? a note: vcm is the common-mode voltage on cp0+ and cp0?. rev. 1.0 55 c8051f70x/71x 10. 10-bit adc (adc0) adc0 on the c8051f700/2/4/6/8 and c8051f710/2/4/6 is a 500 ksps, 10-bit successive-approximation- register (sar) adc with integrated track-and-hold, a gain stage programmable to 1x or 0.5x, and a pro- grammable window detector. the adc is fully configur able under software control via special function registers. the adc may be configured to measure various different signals using the analog multiplexer described in section ?10.5. adc0 analog multiplexer? on page 65. the voltage reference for the adc is selected as described in section ?11. temperature sensor? on page 67. the adc0 subsystem is enabled only when the ad0en bit in the ad c0 control register (a dc0cn) is set to logic 1. the adc0 subsystem is in low power shutdown when this bit is logic 0. figure 10.1. adc0 functional block diagram adc0cf amp0gn0 ad08be ad0ljst ad0sc0 ad0sc1 ad0sc2 ad0sc3 ad0sc4 10-bit sar adc ref sysclk adc0h 32 adc0cn ad0cm0 ad0cm1 ad0cm2 ad0wint ad0busy ad0int ad0tm ad0en timer 0 overflow timer 2 overflow timer 1 overflow start conversion 000 ad0busy (w) vdd adc0lth ad0wint 001 010 011 100 cnvstr input window compare logic 101 timer 3 overflow adc0ltl adc0gth adc0gtl adc0l ain from amux0 x1 or x0.5 amp0gn0 c8051f70x/71x 56 rev. 1.0 10.1. output code formatting the adc measures the input voltage with reference to gnd. the registers adc0h and adc0l contain the high and low bytes of the output conversion code from the adc at the completion of each conversion. data can be right-justified or left-justified, depending on the setting of the ad0ljst bit. conversion codes are represented as 10-bit unsigned integers. inputs are measured from 0 to vref x 1023/1024. example codes are shown below for both right-justified and left -justified data. unused bits in the adc0h and adc0l registers are set to 0. 10.2. 8-bit mode setting the adc08be bit in register adc0cf to 1 will put the adc in 8-bit mode. in 8-bit mode, only the 8 msbs of data are converted, and the adc0h register holds the results. the ad0ljst bit is ignored for 8- bit mode. 8-bit conversions take two fewer sar clock cycles than 10-bit conversions, so the conversion is completed faster, and a 500 ksps sampling rate can be achieved with a slower sar clock. 10.3. modes of operation adc0 has a maximum conversion speed of 500 ksps. the adc0 conversion clock is a divided version of the system clock, determined by the ad0sc bits in the adc0cf register. 10.3.1. starting a conversion a conversion can be initiated in one of six ways, depending on the programmed states of the adc0 start of conversion mode bits (ad0cm2 ? 0) in register adc0cn. conversions may be initiated by one of the fol- lowing: 1. writing a 1 to the ad0busy bit of register adc0cn 2. a timer 0 overflow (i.e., ti med continuous conversions) 3. a timer 2 overflow 4. a timer 1 overflow 5. a rising edge on the cnvstr input signal 6. a timer 3 overflow writing a 1 to ad0busy provides software contro l of adc0 whereby conversions are performed "on- demand". during conversion, the ad0busy bit is set to logic 1 and reset to logic 0 when the conversion is complete. the falling edge of ad0bu sy triggers an interrupt (when enabl ed) and sets the adc0 interrupt flag (ad0int). when polling for adc conversion comp letions, the adc0 interrup t flag (ad0int) should be used. converted data is available in the adc0 data registers, adc0h:adc0l, wh en bit ad0int is logic 1. when timer 2 or timer 3 overflows are used as the conversion source, low byte overflows are used if timer 2/3 is in 8-bit mode; high byte overflows are used if timer 2/3 is in 16-bit mode. see section ?33. timers? on page 262 for timer configuration. important note about using cnvstr: the cnvstr input pin also functions as a port i/o pin. when the cnvstr input is used as t he adc0 conversion source, the associated pin should be skipped by the digi- tal crossbar. see section ?28. port input/output? on page 180 for details on port i/o configuration. input voltage right-justified adc0h:adc0l (ad0ljst = 0) left-justified adc0h:adc0l (ad0ljst = 1) vref x 1023/1024 0x03ff 0xffc0 vref x 512/1024 0x0200 0x8000 vref x 256/1024 0x0100 0x4000 0 0x0000 0x0000 rev. 1.0 57 c8051f70x/71x 10.3.2. tracking modes the ad0tm bit in register adc0cn enables "delayed conversions", and will delay the actual conversion start by three sar clock cycles, during which time t he adc will continue to track th e input. if ad0tm is left at logic 0, a conversion will begin im mediately, without the extra tracking time. for internal start-of-conver- sion sources, the adc will track anyt ime it is not pe rforming a conver sion. when the cnvstr signal is used to initiate conversions, adc0 will track either when ad0tm is logic 1, or when ad0tm is logic 0 and cnvstr is held low. see figure 10.2 for track and convert timing details. delayed conversion mode is useful when amux settings are frequently changed, due to the settling time requirements described in section ?10.3.3. settling time requirements? on page 58. figure 10.2. 10-bit adc track and conversion example timing write '1' to ad0busy, timer 0, timer 2, timer 1 overflow (ad0cm[2:0]=000, 001, 010, 011) ad0tm=1 track convert track ad0tm=0 track or convert convert track sar clocks sar clocks b. adc timing for in ternal trigger source cnvstr (ad0cm[2:0]=1xx) ad0tm=1 a. adc timing for exte rnal trigger source track convert n/c ad0tm=0 track convert track *conversion ends at rising edge of 12 th clock in 8-bit mode *conversion ends at rising edge of 15 th clock in 8-bit mode *conversion ends at rising edge of 12 th clock in 8-bit mode 123456789 10 11 12* 13 14 123456789 10 11 12 13 14 15* 16 17 n/c sar clocks *conversion ends at rising edge of 15 th clock in 8-bit mode sar clocks 123456789 10 11 12 13 14 15* 16 17 123456789 10 11 12* 13 14 c8051f70x/71x 58 rev. 1.0 10.3.3. settling time requirements a minimum tracking time is required before each conversi on to ensure that an accurate conversion is per- formed. this tracking time is determined by any se ries impedance, including the amux0 resistance, the the adc0 sampling capacitance, and the accuracy required for the conversion. in delayed tracking mode, three sar clocks are used for tracking at the start of every conversion. for many applications, these three sar clocks will meet the minimum tracking time requirements. figure 10.3 shows the equivalent adc0 input circuit. the required adc0 settling time for a given settling accuracy (sa) may be approximated by equation 10.1. see table 9.10 for adc0 minimum settling time requirements as well as the mux impedance and sampling capacitor values. equation 10.1. adc0 settling time requirements where: sa is the settling accuracy, given as a fraction of an lsb (for example, 0.25 to settle within 1/4 lsb) t is the required settling time in seconds r total is the sum of the amux0 resistance and any external source resistance. n is the adc resolution in bits (10). figure 10.3. adc0 equivalent input circuits t 2 n sa ------ - ?? ?? r total c sample ? r mux c sample rc input = r mux * c sample mux select input pin note: see electrical spec ification tables for r mux and c sample parameters. rev. 1.0 59 c8051f70x/71x sfr address = 0xbc; sfr page = f sfr definition 10.1. adc0c f: adc0 configuration bit76543210 name ad0sc[4:0] ad0ljst ad08be amp0gn0 type r/w r/w r/w r/w reset 11111001 bit name function 7:3 ad0sc[4:0] adc0 sar conversion cl ock period bits. sar conversion clock is derived from syste m clock by the following equation, where ad0sc refers to the 5-bit value held in bits ad0sc4 ? 0. sar conversion clock requirements are given in the adc specification table. 2ad0ljst adc0 left justify select. 0: data in adc0h:adc0l re gisters are right-justified. 1: data in adc0h:adc0l re gisters are left-justified. note: the ad0ljst bit is only valid for 10-bit mode (ad08be = 0). 1ad08be 8-bit mode enable. 0: adc operates in 10-bit mode (normal). 1: adc operates in 8-bit mode. note: when ad08be is set to 1, the ad0ljst bit is ignored. 0amp0gn0 adc gain control bit. 0: gain = 0.5 1: gain = 1 ad0sc sysclk clk sar ------------ ---------- -1 ? = c8051f70x/71x 60 rev. 1.0 sfr address = 0xbe; sfr page = 0 sfr address = 0xbd; sfr page = 0 sfr definition 10.2. adc0h: adc0 data word msb bit76543210 name adc0h[7:0] type r/w reset 00000000 bit name function 7:0 adc0h[7:0] adc0 data word high-order bits. for ad0ljst = 0: bits 7:2 will read 000000b. bits 1 ? 0 are the upper 2 bits of the 10- bit adc0 data word. for ad0ljst = 1: bits 7:0 are the most-significant bits of the 10-bit adc0 data word. note: in 8-bit mode ad0ljst is ignored, and adc0h holds the 8-bit data word. sfr definition 10.3. adc0l: adc0 data word lsb bit76543210 name adc0l[7:0] type r/w reset 00000000 bit name function 7:0 adc0l[7:0] adc0 data word low-order bits. for ad0ljst = 0: bits 7:0 are the lo wer 8 bits of the 10-bit data word. for ad0ljst = 1: bits 7:6 are the lower 2 bits of the 10-bit data word. bits 5 ? 0 will always read 0. note: in 8-bit mode ad0ljst is ignored, and adc0l will read back 00000000b. rev. 1.0 61 c8051f70x/71x sfr address = 0xe8; sfr page = all pages; bi t-addressable sfr definition 10.4. adc0cn: adc0 control bit76543210 name ad0en ad0tm ad0int ad0busy ad0wint ad0cm[2:0] type r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7ad0en adc0 enable bit. 0: adc0 disabled. adc0 is in low-power shutdown. 1: adc0 enabled. adc0 is active and ready for data conversions. 6ad0tm adc0 track mode bit. 0: normal track mode: when adc0 is ena bled, tracking is continuous unless a con- version is in progress. conversion begins immediately on start-of-conversion event, as defined by ad0cm[2:0]. 1: delayed track mode: when adc0 is enabled, input is tracked when a conversion is not in progress. a start-of-conversion sign al initiates three sar clocks of additional tracking, and then begins the conversion. 5ad0int adc0 conversion comple te interrupt flag. 0: adc0 has not completed a data conv ersion since ad0int was last cleared. 1: adc0 has completed a data conversion. 4ad0busy adc0 busy bit. read: 0: adc0 conversion is not in progress. 1: adc0 conversion is in progress. write: 0: no effect. 1: initiates adc0 conver- sion if ad0cm[2 : 0] = 000b 3 ad0wint adc0 window compare interrupt flag. 0: adc0 window comparison data match ha s not occurred since this flag was last cleared. 1: adc0 window comparison data match has occurred. 2:0 ad0cm[2:0] adc0 start of conversion mode select. 000: adc0 start-of-conversion s ource is write of 1 to ad0busy. 001: adc0 start-of-conversion source is overflow of timer 0. 010: adc0 start-of-conversion source is overflow of timer 2. 011: adc0 start-of-conversion source is overflow of timer 1. 100: adc0 start-of-conversion source is rising edge of external cnvstr. 101: adc0 start-of-conversion source is overflow of timer 3. 11x: reserved. c8051f70x/71x 62 rev. 1.0 10.4. programmable window detector the adc programmable window detector continuously compares the adc0 output registers to user-pro- grammed limits, and notifies the system when a desired condition is detected. this is especially effective in an interrupt-driven system, saving code space and cpu bandwidth while delivering faster system response times. the window detector interrupt flag (ad0wint in register adc0cn) can also be used in polled mode. the adc0 greater-than (adc0gth, adc0gtl) and less-than (adc0lth, adc0ltl) registers hold the comparison valu es. the window detector flag can be programmed to indicate when mea- sured data is inside or outside of the user-progr ammed limits, depending on the contents of the adc0 less-than and adc0 greater-than registers. sfr address = 0xc4; sfr page = 0 sfr address = 0xc3; sfr page = 0 sfr definition 10.5. adc0gth: adc0 greater-than data high byte bit76543210 name adc0gth[7:0] type r/w reset 11111111 bit name function 7:0 adc0gth[7:0] adc0 greater-than data word high-order bits. sfr definition 10.6. adc0gtl: adc 0 greater-than data low byte bit76543210 name adc0gtl[7:0] type r/w reset 11111111 bit name function 7:0 adc0gtl[7:0] adc0 greater-than data word low-order bits. rev. 1.0 63 c8051f70x/71x sfr address = 0xc6; sfr page = 0 sfr address = 0xc5; sfr page = 0 sfr definition 10.7. adc0lth: adc0 less-than data high byte bit76543210 name adc0lth[7:0] type r/w reset 00000000 bit name function 7:0 adc0lth[7:0] adc0 less-than data word high-order bits. sfr definition 10.8. adc0ltl: a dc0 less-than data low byte bit76543210 name adc0ltl[7:0] type r/w reset 00000000 bit name function 7:0 adc0ltl[7:0] adc0 less-than data word low-order bits. c8051f70x/71x 64 rev. 1.0 10.4.1. window de tector example figure 10.4 shows two example window comparisons for right-justified data, with adc0lth:adc0ltl = 0x0080 (128d) and adc0gth:adc0gtl = 0x0040 (64d). the input voltage can range from 0 to vref x (1023/1024) with respect to gnd, and is represented by a 10-bit unsigned integer value. in the left example, an ad0wint interrup t will be generated if th e adc0 conversion word (adc0h:adc0l) is within the range defined by adc0gth:adc0gtl and adc0lth:adc0ltl (if 0x0040 < adc0h:adc0l < 0x0080). in the right exam ple, and ad0wint interr upt will be generated if the adc0 conversion word is outside of the range defined by the adc0gt and adc0lt registers (if adc0h:adc0l < 0x0040 or adc0h:adc0l > 0x0080). figure 10.5 shows an example using left-justi- fied data with the same comparison values. figure 10.4. adc window compare example: right-justified data figure 10.5. adc window compare example: left-justified data 0x03ff 0x0081 0x0080 0x007f 0x0041 0x0040 0x003f 0x0000 0 input voltage (ain - gnd) vref x (1023/ 1024) vref x (128/1024) vref x (64/1024) ad0wint=1 ad0wint not affected ad0wint not affected adc0lth:adc0ltl adc0gth:adc0gtl 0x03ff 0x0081 0x0080 0x007f 0x0041 0x0040 0x003f 0x0000 0 input voltage (ain - gnd) vref x (1023/ 1024) vref x (128/1024) vref x (64/1024) ad0wint not affected ad0wint=1 ad0wint=1 adc0h:adc0l adc0h:adc0l adc0gth:adc0gtl adc0lth:adc0ltl 0xffc0 0x2040 0x2000 0x1fc0 0x1040 0x1000 0x0fc0 0x0000 0 input voltage (ain - gnd) vref x (1023/ 1024) vref x (128/1024) vref x (64/1024) ad0wint=1 ad0wint not affected ad0wint not affected adc0lth:adc0ltl adc0gth:adc0gtl 0xffc0 0x2040 0x2000 0x1fc0 0x1040 0x1000 0x0fc0 0x0000 0 input voltage (ain - gnd) vref x (1023/ 1024) vref x (128/1024) vref x (64/1024) ad0wint not affected ad0wint=1 ad0wint=1 adc0h:adc0l adc0h:adc0l adc0lth:adc0ltl adc0gth:adc0gtl rev. 1.0 65 c8051f70x/71x 10.5. adc0 analog multiplexer adc0 on the c8051f700/2/4/6/8 and c8051f710/2/4/6 uses an analog input multiplexer to select the pos- itive input to the adc. any of the following may be sele cted as the positive input: po rt 0 or port 1 i/o pins, the on-chip temperature sensor, or the positive power supply (v dd ). the adc0 input channel is selected in the adc0mx register described in sfr definition 10.9. figure 10.6. adc0 multiplexer block diagram important note about adc0 input configuration: port pins selected as adc0 inputs should be config- ured as analog inputs, and should be skipped by th e digital crossbar. to configure a port pin for analog input, set the corresponding bit in register pnmdin to 0. to force the crossbar to skip a port pin, set the corresponding bit in register pnskip to 1. see section ?28. port input/output? on page 180 for more port i/o configuration details. adc0 temp sensor amux vreg output adc0mx amx0p4 amx0p3 amx0p2 amx0p1 amx0p0 p0.0 p1.7 vdd gnd c8051f70x/71x 66 rev. 1.0 sfr address = 0xbb; sfr page = 0 sfr definition 10.9. adc0mx: amux0 channel select bit76543210 name amx0p[4:0] type rrr r/w reset 00011111 bit name function 7:5 unused read = 000b; write = don?t care. 4:0 amx0p[4:0] amux0 positive input selection. 64-pin devices 48-pin devices 32-pin devices 00000 p0.0 p0.0 ? 00001 p0.1 p0.1 ? 00010 p0.2 p0.2 ? 00011 p0.3 p0.3 p0.3 00100 p0.4 p0.4 p0.4 00101 p0.5 p0.5 p0.5 00110 p0.6 p0.6 ? 00111 p0.7 p0.7 ? 01000 p1.0 p1.0 ? 01001 p1.1 p1.1 ? 01010 p1.2 p1.2 ? 01011 p1.3 p1.3 ? 01100 p1.4 ? ? 01101 p1.5 ? ? 01110 p1.6 ? ? 01111 p1.7 ? ? 10000 temp sensor temp sensor temp sensor 10001 vreg output vreg output vreg output 10010 vdd vdd vdd 10011 gnd gnd gnd 10100 ? 11111 no input selected rev. 1.0 67 c8051f70x/71x 11. temperature sensor an on-chip temperature sensor is included on the c8051f700/2/4/6/8 and c805 1f710/2/4/6 which can be directly accessed via the adc multiplexer in single- ended configuration. to use the adc to measure the temperature sensor, the adc mux channel should be configured to connect to the temperature sensor. the temperature sensor transfer function is shown in figure 11.1. the output voltage (v temp ) is the posi- tive adc input when the adc multiple xer is set correctly. the tempe bi t in register ref0cn enables/dis- ables the temperature sensor, as described in sfr de finition 12.1. while disabled, the temperature sensor defaults to a high impedance state and any adc me asurements performed on the sensor will result in meaningless data. refer to table 9.12 for the slope and offset parameters of the temperature sensor. figure 11.1. temperature sensor transfer function 11.1. calibration the uncalibrated temperature sensor output is extrem ely linear and suitable for relative temperature mea- surements (see table 5.1 for linearity specificati ons). for absolute temperature measurements, offset and/or gain calibration is recommended. typically a 1-po int (offset) calibration incl udes the following steps: 1. control/measure the ambient temperatur e (this temperature must be known). 2. power the device, and delay for a few seconds to allow for self-heating. 3. perform an adc conversion with the temperat ure sensor selected as the adc?s input. 4. calculate the offset characteristics, and store this value in non-volatile memory for use with subsequent temperature sensor measurements. figure 5.3 shows the typical tem perature sensor error assuming a 1-point calibration at 0 c. temperature voltage v temp = ( slope x temp c ) + offset offset (v at 0 celsius) slope (v / deg c) temp c = (v temp - offset ) / slope c8051f70x/71x 68 rev. 1.0 parameters that affect adc measurem ent, in particular the voltage refer ence value, will also affect temper- ature measurement. figure 11.2. temperature sensor error with 1-point calibration at 0 celsius -40.00 -20.00 0.00 20.00 40.00 60.00 80.00 temperature (degrees c) error (degrees c) -5.00 -4.00 -3.00 -2.00 -1.00 0.00 1.00 2.00 3.00 4.00 5.00 -5.00 -4.00 -3.00 -2.00 -1.00 0.00 1.00 2.00 3.00 4.00 5.00 rev. 1.0 69 c8051f70x/71x 12. voltage and ground reference options the voltage reference mux is configurable to use an externally connected voltage reference, the on-chip voltage reference, or one of two power supply voltages (see figure 12.1). the ground reference mux allows the ground reference for adc0 to be selected between the ground pin (gnd) or a port pin dedi- cated to analog ground (p0.1/agnd). the voltage and ground reference options are configured using the ref0cn sfr described on page 71. electrical specifications are can be found in the electrical specifications chapter. important note about the v ref and agnd inputs: port pins are used as the external v ref and agnd inputs. when using an external voltage reference, p0 .0/vref should be configured as an analog input and skipped by the digital crossbar. when using agnd as the ground reference to adc0, p0.1/agnd should be configured as an analog input and skipped by the digital crossbar. refer to section ?28. port input/out- put? on page 180 for complete port i/o configuration de tails. the external reference voltage must be within the range 0 ? v ref ? v dd and the external ground reference must be at the same dc voltage potential as gnd. figure 12.1. voltage reference functional block diagram p0.0/vref r1 vdd external voltage reference circuit gnd 00 01 10 11 ref0cn refsl0 tempe biase refsl1 refgnd recommended bypass capacitors + 4.7 uf 0.1 uf internal 1.8 v regulated digital supply v dd internal 1.6 v high speed reference gnd p0.1/agnd refgnd 0 1 to analog mux temp sensor en bias generator to adc, internal oscillator, reference, tempsensor en ioscen c8051f70x/71x 70 rev. 1.0 12.1. external voltage references to use an external voltage refer ence, refsl[1:0] should be set to 00. bypass capacitors should be added as recommended by the manufacturer of the external voltage reference. 12.2. internal voltage reference options a 1.6 v high-speed reference is included on-chip. the high speed internal reference is selected by setting refsl[1:0] to 11. when selected, the high-speed internal reference will be automa tically enabled on an as-needed basis by adc0. for applications with a non-varying power supply voltage, using the power supply as the voltage reference can provide adc0 with added dynamic range at the cost of reduced power supply noise rejection. to use the 1.8 to 3.6 v power supply voltage (v dd ) or the 1.8 v regulated digital supply voltage as the reference source, refsl[1:0] should be set to 01 or 10, respectively. 12.3. analog ground reference to prevent ground noise generated by switching digi tal logic from affecting sensitive analog measure- ments, a separate analog ground reference option is available. when enabled, the ground reference for adc0 is taken from the p0.1/agnd pin. any external sensors sampled by adc0 should be referenced to the p0.1/agnd pin. the separate analog ground re ference option is enabled by setting refgnd to 1. note that when using this option, p0.1/agnd mu st be connected to the same potential as gnd. 12.4. temperature sensor enable the tempe bit in register ref0cn enables the temper ature sensor. while disabled, the temperature sen- sor defaults to a high impedance state and any adc0 measurements performed on the sensor result in meaningless data. rev. 1.0 71 c8051f70x/71x sfr address = 0xd2; sfr page = f sfr definition 12.1. ref0cn: voltage reference control bit76543210 name refgnd refsl tempe biase type r r r/w r/w r/w r/w r/w r reset 00010000 bit name function 7:6 unused read = 00b; write = don?t care. 5refgnd analog ground reference. selects the adc0 ground reference. 0: the adc0 ground reference is the gnd pin. 1: the adc0 ground reference is the p0.1/agnd pin. 4:3 refsl voltage reference select. selects the adc0 voltage reference. 00: the adc0 voltage reference is the p0.0/vref pin. 01: the adc0 voltage reference is the vdd pin. 10: the adc0 voltage reference is the internal 1.8 v digital supply voltage. 11: the adc0 voltage reference is the internal 1.6 v high-speed voltage reference. 2 tempe temperature sensor enable. enables/disables the internal temperature sensor. 0: temperature sensor disabled. 1: temperature sensor enabled. 1 biase internal analog bias generator enable bit. 0: internal bias generator off. 1: internal bias generator on. 0 unused read = 0b; write = don?t care. c8051f70x/71x 72 rev. 1.0 13. voltage regulator (reg0) c8051f70x/71x devices include an internal voltage regulator (reg0) to regulate the internal core supply to 1.8 v from a v dd supply of 1.8 to 3.6 v. two power-saving modes are built into the regulator to help reduce current consumption in low-power applicat ions. these modes are accessed through the reg0cn register (sfr definition 13.1). elec trical characteristics for the on-chi p regulator are specified in table 9.5 on page 50 if an external regulator is used to power the device, the internal regulator may be put into bypass mode using the bypass bit. the internal regulator should never be placed in bypass mode unless an external 1.8 v regulator is used to supply v dd . doing so could cause permanent damage to the device. under default conditio ns, when the device enters stop mode the internal regulato r will remain on. this allows any enabled reset source to generate a reset for the device and bring the device out of stop mode. for additional power savings, the stopcf bit can be used to shut down the regulator and the internal power network of the device when the part enters stop mode. when stopcf is set to 1, the rst pin or a full power cycle of the device are the only methods of generating a reset. rev. 1.0 73 c8051f70x/71x sfr address = 0xb9; sfr page = f sfr definition 13.1. reg0cn: voltage regulator control bit76543210 name stopcf bypass type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7stopcf stop mode configuration. this bit configures the regulator?s be havior when the device enters stop mode. 0: regulator is still active in stop m ode. any enabled reset source will reset the device. 1: regulator is shut down in stop mode. only the rst pin or power cycle can reset the device. 6 bypass bypass internal regulator. this bit places the regulator in bypass mode, allowing the core to ru n directly from the v dd supply pin. 0: normal mode?regulator is on and regulates v dd down to the core voltage. 1: bypass mode?regulator is in bypass mode , and the microcontroller core operates directly from the v dd supply voltage. important: bypass mode is for use with an external regulator as the supply voltage only. never place the regulator in bypass mode when the v dd supply voltage is greater than the specifications given in table 9.1 on page 47. doing so may cause permanent damage to the device. 5:0 reserved reserved. must write 000000b. c8051f70x/71x 74 rev. 1.0 14. comparator0 c8051f70x/71x devices include an on-chip programmable voltage comparator, comparator0, shown in figure 14.1. the comparator offers programmable response time a nd hysteresis, an analog in put multiplexer, and two outputs that are optionally availabl e at the port pins: a synchronous ?latched? output (cp0), or an asyn- chronous ?raw? output (cp0a). the asynchronous cp0a signal is available even when the system clock is not active. this allows the comparator to operate and generate an output with the device in stop mode. when assigned to a port pin, the comparator outpu t may be configured as open drain or push-pull (see section ?28.4. port i/o initialization? on page 189). comparator0 may also be used as a reset source (see section ?25.5. comparator0 reset? on page 167). the comparator0 inputs are selected by the comparator input multiplexer, as detailed in section ?14.1. comparator multiplexer? on page 78. figure 14.1. comparator0 functional block diagram the comparator output can be polled in software, used as an interrupt source, and/or routed to a port pin. when routed to a port pin, the co mparator output is available asyn chronous or synchronous to the system clock; the asynchronous output is available even in stop mode (with no system clock active). when dis- abled, the comparator output (if assigned to a port i/o pin via the crossbar) defaults to the logic low state, and the power supply to the compar ator is turned off. see section ?28.3. priority crossbar decoder? on page 185 for details on configuring comparator outputs via the digital crossbar. comparator inputs can be externally driven from ?0.25 v to (v dd ) + 0.25 v without damage or upset. the complete comparator elec- trical specifications are given in section ?9. electrical characteristics? on page 47. vdd reset decision tree + - crossbar q q set clr d q q set clr d (synchronizer) gnd cp0 + cp0 - cpt0md cp0rie cp0fie cp0md1 cp0md0 cp0 cp0a cp0 interrupt 0 1 0 1 cp0rif cp0fif 0 1 cp0en 0 1 ea comparator input mux cpt0cn cp0en cp0out cp0rif cp0fif cp0hyp1 cp0hyp0 cp0hyn1 cp0hyn0 rev. 1.0 75 c8051f70x/71x the comparator response time may be configured in software via the cpt0md register (see sfr defini- tion 14.2). selecting a longer response time reduces the comparator supply current. figure 14.2. comparator hysteresis plot the comparator hysteresis is software-programmabl e via its comparator cont rol register cpt0cn. the user can program both the amount of hysteresis voltage (referred to the input voltage) and the positive and negative-going symmetry of this hyst eresis around the threshold voltage. the comparator hysteresis is programmed using bits3 ? 0 in the comparator control register cpt0cn (shown in sfr definition 14.1). the amount of negative hysteresis voltage is determined by the settings of the cp0hyn bits. as shown in figure 14.2, settings of 20, 10 or 5 mv of negative hysteresis can be pro- grammed, or negative hysteresis can be disabled. in a similar way, the amount of positive hysteresis is determined by the setting the cp0hyp bits. comparator interrupts can be genera ted on both rising-e dge and falling-edge output transitions. (for inter- rupt enable and priority control, see section ?21.1. mcu interrupt sources and vectors? on page 138). the cp0fif flag is set to logic 1 upon a comparator falling-edge occurrence, and the cp0rif flag is set to logic 1 upon the comparator rising-edge occurrence. once set, these bits remain set until cleared by soft- ware. the comparator rising-edge interrupt mask is enabled by setting cp0rie to a logic 1. the comparator0 falling-edge interrupt mask is enabled by setting cp0fie to a logic 1. the output state of the comparator can be obtained at any time by reading the cp0out bit. the compar- ator is enabled by setting the cp0en bit to logic 1, and is disabled by clearing this bit to logic 0. note that false rising ed ges and falling edges can be detected when the comparator is first powered on or if changes are made to the hy steresis or response time control bits. therefore, it is recommended that the rising-edge and falling-edge flags be explicitly cleared to logic 0 a short time after the comparator is enabled or its mode bits have been changed. positive hysteresis voltage (programmed with cp0hyp bits) negative hysteresis voltage (programmed by cp0hyn bits) vin- vin+ inputs circuit configuration + _ cp0+ cp0- cp0 vin+ vin- out v oh positive hysteresis disabled maximum positive hysteresis negative hysteresis disabled maximum negative hysteresis output v ol c8051f70x/71x 76 rev. 1.0 sfr address = 0x9b; sfr page = 0 sfr definition 14.1. cpt0 cn: comparator0 control bit76543210 name cp0en cp0out cp0rif cp0fif cp0hyp[1:0] cp0hyn[1:0] type r/w r r/w r/w r/w r/w reset 00000000 bit name function 7 cp0en comparator0 enable bit. 0: comparator0 disabled. 1: comparator0 enabled. 6cp0out comparator0 output state flag. 0: voltage on cp0+ < cp0 ? . 1: voltage on cp0+ > cp0 ? . 5cp0rif comparator0 rising-edge flag. must be cleared by software. 0: no comparator0 rising edge has occurred since this flag was last cleared. 1: comparator0 rising edge has occurred. 4cp0fif comparator0 falling-edge flag. must be cleared by software. 0: no comparator0 falling-edge has occu rred since this flag was last cleared. 1: comparator0 falling- edge has occurred. 3:2 cp0hyp[1:0] comparator0 positive hysteresis control bits. 00: positive hysteresis disabled. 01: positive hysteresis = 5 mv. 10: positive hysteresis = 10 mv. 11: positive hysteresis = 20 mv. 1:0 cp0hyn[1:0] comparator0 negative hysteresis control bits. 00: negative hysteresis disabled. 01: negative hysteresis = 5 mv. 10: negative hysteresis = 10 mv. 11: negative hysteresis = 20 mv. rev. 1.0 77 c8051f70x/71x sfr address = 0x9d; sfr page = 0 sfr definition 14.2. cpt0md: comparator0 mode selection bit76543210 name cp0rie cp0fie cp0md[1:0] type rrr/wr/wrr r/w reset 00000010 bit name function 7:6 unused read = 00b, write = don?t care. 5cp0rie comparator0 rising-edge interrupt enable. 0: comparator0 rising-edge interrupt disabled. 1: comparator0 rising-edge interrupt enabled. 4cp0fie comparator0 falling-edge interrupt enable. 0: comparator0 falling-edge inte rrupt disabled. 1: comparator0 falling-edge inte rrupt enabled. 3:2 unused read = 00b, write = don?t care. 1:0 cp0md[1:0] comparator0 mode select. these bits affect the response time and power consumption for comparator0. 00: mode 0 (fastest response time, highest power consumption) 01: mode 1 10: mode 2 11: mode 3 (slowest response time, lowest power consumption) c8051f70x/71x 78 rev. 1.0 14.1. comparator multiplexer c8051f70x/71x devices include an analog input multip lexer to connect port i/o pins to the comparator inputs. the comparator0 inputs are selected in the cpt0mx register (sfr definition 14.3). the cmx0p2 ? cmx0p0 bits select the comparator0 positive input; the cmx0n2 ? cmx0n0 bits select the comparator0 negative input. important note about comparator inputs: the port pins selected as comparator inputs should be con- figured as analog inputs in their associated port co nfiguration register, and configured to be skipped by the crossbar (for details on port configuration, see se ction ?28.6. special function registers for accessing and configuring port i/o? on page 194). figure 14.3. comparator input multiplexer block diagram - + cp0 - cp0 + cpt0mx cmx0p0 cmx0p1 cmx0p2 cmx0n2 cmx0n1 cmx0n0 gnd vdd p1.0 p1.2 p1.4 p1.6 p1.1 p1.3 p1.5 p1.7 / p2.0* *p1.7 on 64 and 48-pin devices, p2.0 on 32 and 24-pin devices rev. 1.0 79 c8051f70x/71x sfr address = 0x9f; sfr page = 0 sfr definition 14.3. cpt0mx: comparator0 mux selection bit76543210 name cmx0n[2:0] cmx0p[2:0] type rr/wrr/w reset 00000000 bit name function 7 unused read = 0b; write = don?t care. 6:4 cmx0n[2:0] comparator0 negative input mux selection. 64-pin devices 48-pin devices 32-pin devices 24-pin devices 000 p1.1 p1.1 ? ? 001 p1.3 p1.3 ? ? 010 p1.5 ? ? ? 011 p1.7 ? p2.0 (see note) p2.0 (see note) 100-111 no input selected. no input selected. no input selected. no input selected. 3 unused read = 0b; write = don?t care. 2:0 cmx0p[2:0] comparator0 positive input mux selection. 64-pin devices 48-pin devices 32-pin devices 24-pin devices 000 p1.0 p1.0 ? ? 001 p1.2 p1.2 ? ? 010 p1.4 ? ? ? 011 p1.6 ? (p1.6?see note) (p1.6?see note) 100-111 no input selected. no input selected. no input selected. no input selected. note: on 32 and 24-pin devices, p2.0 can be used as the neg ative comparator input, for detecting low-level signals near the gnd or vdd supply rails. the p1.6 setting for the positive input should be used in conjunction with the selection of p2.0 as the negative input. p1.6 should be configured for push-pull mode and driven to the desired supply rail. although p1.6 is not connected to a dev ice pin in these packages, it is still a valid signal internally. c8051f70x/71x 80 rev. 1.0 15. capacitive sense (cs0) the capacitive sense subsystem uses a capacitance-to -digital circuit to determine the capacitance on a port pin. the module can take measurements from different port pins using the module?s analog multi- plexer. the module is enabled only when the cs0en bit (cs0cn) is set to 1. otherwise the module is in a low-power shutdown state. the module can be configured to take measurements on one port pin or a group of port pins, using auto-scan. a selectable gai n circuit allows the designer to adjust the maximum allowable capacitance. an accumulator is also included, which can be configured to average multiple con- versions on an input channel. interrupts can be gene rated when cs0 completes a conversion or when the measured value crosses a threshold defined in cs0thh:l. figure 15.1. cs0 block diagram capacitance to digital converter timer 0 overflow timer 2 overflow timer 1 overflow start conversion 000 cs0busy (w) cs0cmpf 001 010 011 100 timer 3 overflow greater than compare logic 101 initiated continuously cs0thh:l cs0dh:l auto-scan logic cs0ss cs0se cs0mx 22-bit accumulator 110 111 initiated continuously when auto-scan enabled reserved cs0cn cs0cmpf cs0cmpen cs0busy cs0int cs0pme cs0en cs0cf cs0acu0 cs0acu1 cs0acu2 cs0cm0 cs0cm1 cs0cm2 amux . . . 1x-8x cs0md1 cs0cg0 cs0cg1 cs0cg2 cs0dr0 cs0dr1 cs0md2 cs0ia0 cs0ia1 cs0ia2 cs0dt0 cs0dt1 cs0dt2 cs0cr0 cs0cr1 cs0pm cspmmd0 cspmmd1 cp0pm piopm pcapm smbpm spipm uapm pin monitor port i/o and peripherals 12, 13, 14, or 16 bits rev. 1.0 81 c8051f70x/71x 15.1. configuring port pi ns as capacitive sense inputs in order for a port pin to be measured by cs0, that port pin must be configured as an analog input (see ?28. port input/output ? ). configuring the input mult iplexer to a port pin not conf igured as an analog input will cause the capacitance-to-digital converter to output incorrect measurements. note: when cs0 begins a conversion to measure capacitance on a port pin, cs0 grounds all other port pins that meet the following requirements: - the port pin is accessible by the cs0 input multiplexer. - the port pin is configured as an analog input. - the port latch contains a 0. 15.2. cs0 gain adjustment the gain of the cs0 circuit can be adjusted in integer increments from 1x to 8x (8x is the default). high gain gives the best sensitivity and resolution for small capacitors, such as those typically implemented as touch-sensitive pcb features. to measure larger capa citance values, the gain can be lowered. however, lower gain values will affect the overall conversion time. seetable 15.1 for more details on the gain adjust- ment. the bits cs0cg[2:0] in regi ster cs0md1 set the gain value. 15.3. capacitive sense start-of-conversion sources a capacitive sense conversion can be initiated in one of seven ways, depending on the programmed state of the cs0 start of conversion bits (cs0cf6:4). conversions may be initiated by one of the following: 1. writing a 1 to the cs0busy bit of register cs0cn 2. timer 0 overflow 3. timer 2 overflow 4. timer 1 overflow 5. timer 3 overflow 6. convert continuously 7. convert continuously with auto-scan enabled table 15.1. gain setting vs. maximum capacitance and conversion time cs0cg[2:0] (gain) maximum total capacitance (pf) 1 conversion time (s) 2 000b (1x) 520 178 001b (2x) 260 93 010b (3x) 175 66 011b (4x) 130 52 100b (5x) 105 43 101b (6x) 85 38 110b (7x) 75 34 111b (8x) 65 31 notes: 1. the maximum total capacitance values listed in this tabl e are for guidance only, and are not a specification. the total measured capacitance will incl ude internal capacitance as well as external parasitics, and the actual external capacitance being measured. please refer to the electrical specifications for details on the maximum external capacitance. 2. conversion times are nominal, and listed for 13-bit conv ersions with all other cs0 settings at their default values. c8051f70x/71x 82 rev. 1.0 if cs0busy is used to initiate conversions, and then polled to determine if the conversion is finished, at least one clock cycle must be in serted between setting cs0busy to 1 and polling the cs0busy bit. conversions can be configured to be initiated cont inuously through one of two methods. cs0 can be con- figured to convert at a single channel continuously or it can be configured to convert continuously with auto-scan enabled. when configured to convert continuously, conver sions will begin after the cs0busy bit in cs0cf has been set. an interrupt will be gen erated if cs0 conversion complete interrupts are enabled by setting the ecscpt bit (eie2.0). the cs0 module uses a method of successive approxim ation to determine the value of an external capac- itance. the number of bits the cs0 module converts is adjustable using the cs0cr bits in register cs0md2. conversions are 13 bits long by default, bu t they can be adjusted to 12, 13, 14, or 16 bits depending on the nee ds of the application. unconverted bits will be set to 0. shorter conv ersion lengths produce faster conversion rates, and vice-versa. applications can take advantage of faster conversion rates when the unconverted bits fall below the noise floor. note: cs0 conversion complete interrupt behavior depends on the settings of the cs0 accumulator. if cs0 is configured to accumulate multiple conversions on an input channel, a cs0 conversion complete interrupt will be generated only after the last conversion completes. rev. 1.0 83 c8051f70x/71x 15.4. automatic scanning cs0 can be configured to automatically scan a sequenc e of contiguous cs0 input channels by configuring and enabling auto-scan. using auto-scan with the cs 0 comparator interrupt enabled allows a system to detect a change in measured capacitance without requiring any additional dedicated mcu resources. auto-scan is enabled by setting the cs0 start-of-con version bits (cs0cf6:4) to 111b. after enabling auto- scan, the starting and ending channels should be set to appropriate values in cs0ss and cs0se, respec- tively. writing to cs0ss when auto- scan is enabled will cause the value wr itten to cs0ss to be copied into cs0mx. after being enabled, writ ing a 1 to cs0busy will start auto-sc an conversions. when auto-scan completes the number of conversions defined in the cs0 accumulator bits (cs0cf2:0), auto-scan config- ures cs0mx to the next sequential po rt pin configured as an analog input and begins a conversion on that channel. the scan sequence continues until cs0mx reaches the ending input channel value defined in cs0se. note: all other cs0 pins configured for analog input with a 0 in the port latch are grounded during the conversion. after the final channel conversion, auto-scan configures cs0mx back to the starting input channel. for an example system configured to use auto-scan, pleas e see figure ?15.2 auto-scan example? on page 83. note: auto-scan attempts one conversion on a cs0mx channel regardless of whether that channel?s port pin has been configured as an analog input. auto-scan will also complete the current rotation when the device is halted for debugging. if auto-scan is enable d when the device enters su spend mode, auto-scan will re main enabled and running. this feature allows the device to wake from susp end through cs0 greater-than comparator event on any configured capacitive sense input included in the auto-scan sequence of inputs. figure 15.2. auto-scan example sfr configuration: a d a a d d d d d a a a a a a a p2.0 pxmdin bit port pin 0 cs0mx channel p2.1 1 p2.2 2 p2.3 3 p2.4 4 p2.5 5 p2.6 6 p2.7 7 p3.0 8 p3.1 9 p3.2 10 p3.3 11 p3.4 12 p3.5 13 p3.6 14 p3.7 15 cs0ss = 0x02 cs0se = 0x0d p2mdin = 0xf2 p3mdin = 0x04 cs0cf = 0x70 cs0cn = 0x80 enables cs0 enables auto-scan as start-of- conversion source sets p2.2 as auto- scan starting channel sets p3.5 as auto- scan ending channel configures p2.3, p2.2, p2.0 as analog inputs configures p3.0-p3.1 and p3.3-p3.7 as analog inputs scans on channels not configured as analog inputs result in indeterminate values that cannot trigger a cs0 greater than interrupt event c8051f70x/71x 84 rev. 1.0 15.5. cs0 comparator the cs0 comparator compares the latest capacitive sense conversion result with the value stored in cs0thh:cs0thl. if the result is less than or equal to the stored value, the cs0cmpf bit(cs0cn:0) is set to 0. if the result is greater than the stored value, cs0cmpf is set to 1. if the cs0 conversion accumulator is configured to accumula te multiple conversion s, a comparison will not be made until the last conversion has been accumulated. an interrupt will be gene rated if cs0 greater-than comparator in terrupts are enabled by setting the ecs- grt bit (eie2.1) when the comparator sets cs0cmpf to 1. if auto-scan is running when the comparator sets the cs0cmpf bit, no further auto-scan initiated conver- sions will start until firmware sets cs0busy to 1. a cs0 greater-than comparator event can wake a device from suspend mode. this feature is useful in sys- tems configured to continuously sa mple one or more capacitive sens e channels. the device will remain in the low-power suspend state until the captured va lue of one of the scanned channels causes a cs0 greater-than comparator event to occur. it is not necessary to have cs0 comparator interrupts enabled in order to wake a device from suspend with a greater-than event. for a summary of behavior with different cs0 comp arator, auto-scan, and auto accumulator settings, please see table 15.2. rev. 1.0 85 c8051f70x/71x 15.6. cs0 conversion accumulator cs0 can be configured to accumulate multiple conversi ons on an input channel. the number of samples to be accumulated is configured using the cs0acu2:0 bi ts (cs0cf2:0). the accumulator can accumulate 1, 4, 8, 16, 32, or 64 samples. after the defined number of samples have been accumulated, the result is divided by either 1, 4, 8, 16, 32, or 64 (depending on the cs0acu[2:0] setting) and copied to the cs0dh:cs0dl sfrs. table 15.2. operation with auto-scan and accumulate auto-scan enabled accumulator enabled cs0 conversion complete interrupt behavior cs0 greater than interrupt behavior cs0mx behavior nn cs0int interrupt serviced after 1 conversion com- pletes interrupt serviced after 1 con- version complete s if value in cs0dh:cs0dl is greater than cs0thh:cs0thl cs0mx unchanged. ny cs0int interrupt serviced after m conversions com- plete interrupt serviced after m con- versions complete if value in cs0dh:cs0dl (post accumu- late and divide) is greater than cs0thh:cs0thl cs0mx unchanged. yn cs0int interrupt serviced after 1 conversion com- pletes interrupt serviced after con- version complete s if value in cs0dh:cs0dl is greater than cs0thh:cs0thl; auto-scan stopped if greater-than comparator detects conver- sion value is greater than cs0thh:cs0thl, cs0mx is left unchanged; otherwise, cs0mx updates to the next channel (cs0mx + 1) and wraps back to cs0ss after passing cs0se yy cs0int interrupt serviced after m conversions com- plete interrupt serviced after m con- versions complete if value in cs0dh:cs0dl (post accumu- late and divide) is greater than cs0thh:cs0thl; auto-scan stopped if greater-than comparator detects conver- sion value is greater than cs0thh:cs0thl, cs0mx is left unchanged; otherwise, cs0mx updates to the next channel (cs0mx + 1) and wraps back to cs0ss after passing cs0se m = accumulator setting (1x, 4x, 8x, 16x, 32x, 64x) c8051f70x/71x 86 rev. 1.0 15.7. cs0 pin monitor the cs0 module provides accurate conversions in all operating modes of the cpu, peripherals and i/o ports. pin monitoring circuits are provided to improv e interference immunity from high-current output pin switching. the capacitive sense pin monitor register (cs0pm, sfr definition 15.9 ) controls the operation of these pin monitors. conversions in the cs0 module are immune to any change on digital inputs and immune to most output switching. even high-speed serial data transmission will not affect cs0 operation as long as the output load is limited. output changes that switch large loads such as leds and heavily-loaded communications lines can affect conversion accuracy. for this reason, the cs0 module includes pin monitoring circuits that will, if enabled, automatically adjust co nversion timing if necessary to e liminate any effect from high-current output pin switching. the pin monitor enable bit should be set for any outp ut signal that is expected to drive a large load. example: the smbus in a system is heavily loaded wit h multiple slaves and a long pcb route. set the smbus pin monitor enable, smbpm = 1. example: timer2 controls an led on port 1, pin 3 to provide variable dimming. set the port sfr write monitor enable, piopm = 1. example: the spi bus is used to communicate to a nearby host. the pin monitor is not needed because the output is not heavily loaded, spipm remains = 0, the default reset state. pin monitors should not be enabled unless they are required. the pin monitor works by repeating any por- tion of a conversion that may have been corrupted by a change on an output pin. setting pin monitor enables bits will slow cs0 conversions. the frequency of cs0 retry operations can be limited by setting the cspmmd bits. in the default (reset) state, all converter retry requests will be performed. this is the recommended setting for all applications. the number of retries per conversion can be limited to either two or four retries by changing cspmmd. limiting the number of retries per conversion ensure s that even in circumstances where extremely fre- quent high-power ou tput switching occurs, conversions will be completed, though there may be some loss of accuracy due to switching noise. activity of the pin monitor circuit c an be detected by reading the pin monitor event bit, cs0pme, in register cs0cn. this bit will be set if any cs 0 converter retries have occurred. it remains se t until cleared by soft- ware or a device reset. rev. 1.0 87 c8051f70x/71x 15.8. adjusting cs0 for special situations there are several configuration options in the cs0 modu le designed to modify the operation of the circuit and address special situations. in particular, any circuit with more than 500 ? of series impedance between the sensor and the device pin may require ad justments for optimal performance. typical applica- tions which may require adju stments include the following: ? touch panel sensors fabricated using a resistive conductor such as indium-tin-oxide (ito). ? circuits using a high-value series resistor to is olate the sensor element for high esd protection. most systems will require no fine tuning, and th e default settings for cs0dt, cs0dr, and cs0ia should be used. c8051f70x/71x 88 rev. 1.0 sfr address = 0x9a; sfr page = 0 sfr definition 15.1. cs0cn: capacitive sense control bit7654 3 210 name cs0en cs0pme cs0int cs0busy cs0cmpen cs0cmpf type r/w r/w r/w r/w r/w r r r reset 0000 0 000 bit name description 7cs0en cs0 enable. 0: cs0 disabled and in low-power mode. 1: cs0 enabled and ready to convert. 6 cs0pme cs0 pin monitor event. set if any converter re-try requests have occurred due to a pin monitor event. this bit remains set until cleared by firmware. 5cs0int cs0 interrupt flag. 0: cs0 has not completed a data conversion since the last time cs0int was cleared. 1: cs0 has completed a data conversion. this bit is not automatically cleared by hardware. 4 cs0busy cs0 busy. read: 0: cs0 conversion is complete or a conversion is not currently in progress. 1: cs0 conversion is in progress. write: 0: no effect. 1: initiates cs0 conversion if cs0cm[2:0] = 000b, 110b, or 111b. 3 cs0cmpen cs0 digital comparator enable bit. enables the digital comparator, which compares accumulated cs0 conversion output to the value stored in cs0thh:cs0thl. 0: cs0 digital comparator disabled. 1: cs0 digital comparator enabled. 2:1 unused read = 00b; write = don?t care 0 cs0cmpf cs0 digital comparator interrupt flag. 0: cs0 result is smaller than the value set by cs0thh and cs0thl since the last time cs0cmpf was cleared. 1: cs0 result is greater than the value set by cs0thh and cs0thl since the last time cs0cmpf was cleared. rev. 1.0 89 c8051f70x/71x sfr address = 0x9e; sfr page = 0 sfr definition 15.2. cs0cf: ca pacitive sense configuration bit76543210 name cs0cm[2:0] cs0acu[2:0] type r r/w r/w r/w r r/w r/w r/w reset 00000000 bit name description 7 unused read = 0b; write = don?t care 6:4 cs0cm[2:0] cs0 start of conversion mode select. 000: conversion initiated on ev ery write of 1 to cs0busy. 001: conversion initiated on overflow of timer 0. 010: conversion initiated on overflow of timer 2. 011: conversion initiated on overflow of timer 1. 100: conversion initiated on overflow of timer 3. 101: reserved. 110: conversion initiated continuously after writing 1 to cs0busy. 111: auto-scan enabled, conversions init iated continuously after writing 1 to cs0busy. 3 unused read = 0b; write = don?t care 2:0 cs0acu[2:0] cs0 accumulator mode select. 000: accumulate 1 sample. 001: accumulate 4 samples. 010: accumulate 8 samples. 011: accumulate 16 samples 100: accumulate 32 samples. 101: accumulate 64 samples. 11x: reserved. c8051f70x/71x 90 rev. 1.0 sfr address = 0xaa; sfr page = 0 sfr address = 0xa9; sfr page = 0 sfr definition 15.3. cs0dh: capa citive sense data high byte bit76543210 name cs0dh[7:0] type rrrrrrrr reset 00000000 bit name description 7:0 cs0dh cs0 data high byte. stores the high byte of the last comp leted 16-bit capacitive sense conversion. sfr definition 15.4. cs0dl: ca pacitive sense data low byte bit76543210 name cs0dl[7:0] type rrrrrrrr reset 00000000 bit name description 7:0 cs0dl cs0 data low byte. stores the low byte of the last comple ted 16-bit capacitive sense conversion. rev. 1.0 91 c8051f70x/71x sfr address = 0x92; sfr page = f sfr address = 0x93; sfr page = f sfr definition 15.5. cs0ss: capaciti ve sense auto-scan start channel bit76543210 name cs0ss[5:0] type rr r/w reset 00000000 bit name description 7:6 unused read = 00b; write = don?t care 5:0 cs0ss[5:0] starting channel for auto-scan. sets the first cs0 channel to be selected by the mux for capacitive sense conver- sion when auto-scan is enabled and active. all channels detailed in cs0mx sfr definition 15.12 are possible choices for this register. when auto-scan is enabled, a writ e to cs0ss will also update cs0mx. sfr definition 15.6. cs0se: capaciti ve sense auto-scan end channel bit76543210 name cs0se[5:0] type rr r/w reset 00000000 bit name description 7:6 unused read = 000b; write = don?t care 5:0 cs0se[5:0] ending channel for auto-scan. sets the last cs0 channel to be selected by the mux for capacitive sense conver- sion when auto-scan is enabled and active. all channels detailed in cs0mx sfr definition 15.12 are possible choices for this register. c8051f70x/71x 92 rev. 1.0 sfr address = 0x97; sfr page = 0 sfr address = 0x96; sfr page = 0 sfr definition 15.7. cs0thh: capacitive sense comparator threshold high byte bit76543210 name cs0thh[7:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name description 7:0 cs0thh[7:0] cs0 comparator threshold high byte. high byte of the 16-bit value compared to the capacitive sense conversion result. sfr definition 15.8. cs0thl: capacitive sense comparator threshold low byte bit76543210 name cs0thl[7:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name description 7:0 cs0thl[7:0] cs0 comparator threshold low byte. low byte of the 16-bit value compared to the capacitive sense conversion result. rev. 1.0 93 c8051f70x/71x sfr address = 0x9f; sfr page = f sfr definition 15.9. cs0pm: ca pacitive sense pin monitor bit76543210 name uapm spipm smbpm pcapm piopm cp0pm cspmmd[1:0] type r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name description 7 uapm uart pin monitor enable. enables monitoring of the uart tx pin. 6 spipm spi pin monitor enable. enables monitoring spi output pins. 5smbpm smbus pin monitor enable. enables monitoring of the smbus pins. 4 pcapm pca pin monitor enable. enables monitoring of pca output pins. 3 piopm port i/o pin monitor enable. enables monitoring of writes to the port latch registers. 2 cp0pm cp0 pin monitor enable. enables monitoring of the comparator cp0 (synchronous) output. 1:0 cspmmd[1:0] cs0 pin monitor mode. selects the operation to take when a monitored signal changes state. 00: always retry bit cycles on a pin state change. 01: retry up to twice on consecutive bit cycles. 10: retry up to four times on consecutive bit cycles. 11: reserved. c8051f70x/71x 94 rev. 1.0 sfr address = 0xad; sfr page = 0 sfr definition 15.10. cs0md1 : capacitive sense mode 1 bit76543210 name cs0dr[1:0] cs0cg[2:0] type r r/w r r/w r/w r/w reset 00000111 bit name description 7:6 unused read = 00b; write = don?t care 5:4 cs0dr[1:0] cs0 double reset select. these bits adjust the secondary cs0 reset time. for most touch-sensitive switches, the default (fastest) value is sufficient, and these bits should not be modified. 00: no additional time is used for secondary reset (recommended for most switches) 01: an additional 0.75 s is used for secondary reset. 10: an additional 1.5 s is used for secondary reset. 11: an additional 2.25 s is used for secondary reset. 3 unused read = 0b; write = don?t care 2:0 cs0cg[2:0] cs0 reference gain select. these bits select the "gain" applied to the current used to charge an internal refer- ence capacitor. lower gain values decr ease the current setting, and increase both the size of the capacitance that can be measured with the cs0 module, and the base conversion time. refer to ?15. 2. cs0 gain adjustment? on page 81 for more information. 000: gain = 1x 001: gain = 2x 010: gain = 3x 011: gain = 4x 100: gain = 5x 101: gain = 6x 110: gain = 7x 111: gain = 8x (default) rev. 1.0 95 c8051f70x/71x sfr address = 0xbe; sfr page = f sfr definition 15.11. cs0md2 : capacitive sense mode 2 bit76543210 name cs0cr[1:0] cs0dt[ 2:0] cs0ia[2:0] type r/w r/w r/w reset 01000000 bit name description 7:6 cs0cr[1:0] cs0 conversion rate. these bits control the conversion rate of the cs0 module. see the electrical spec- ifications table for specific timing. 00: conversions last 12 internal cs0 clocks and are 12 bits in length. 01: conversions last 13 internal cs0 clocks and are 13 bits in length. 10: conversions last 14 internal cs0 clocks and are 14 bits in length. 11: conversions last 16 internal cs0 clocks.and are 16 bits in length. 5:3 cs0dt[2:0] cs0 discharge time. these bits adjust the primary cs0 reset time. for most touch-sensitive switches, the default (fastest) value is sufficient, and these bits should not be modified. 000: discharge time is 0.75 s (recommended for most switches) 001: discharge time is 1.0 s 010: discharge time is 1.2 s 011: discharge time is 1.5 s 100: discharge time is 2 s 101: discharge time is 3 s 110: discharge time is 6 s 111: discharge time is 12 s 2:0 cs0ia[2:0] cs0 output curre nt adjustment. these bits allow the user to adjust the ou tput current used to charge up the capac- itive sensor element. for mo st touch-sensitive switches, the default (highest) cur- rent is sufficient, and these bits should not be modified. 000: full current (recommended for most switches) 001: 1/8 current 010: 1/4 current 011: 3/8 current 100: 1/2 current 101: 5/8 current 110: 3/4 current 111: 7/8 current c8051f70x/71x 96 rev. 1.0 15.9. capacitive sense multiplexer the input multiplexer can be controlled through two methods. the cs0mx register can be written to through firmware, or the register can be configured automatically using the modu les auto-scan functionality (see ?15.4. automatic scanning? ). figure 15.3. cs0 multiplexer block diagram cs0 cs0mux cs0mx cs0uc cs0mx5 cs0mx4 cs0mx3 cs0mx2 cs0mx1 cs0mx0 p2.0 p6.5 rev. 1.0 97 c8051f70x/71x sfr address = 0x9c; sfr page = 0 sfr definition 15.12. cs0mx: cap acitive sense mux channel select bit76543210 name cs0uc cs0mx[5:0] type r/w r/w r/w reset 00000000 bit name description 7cs0uc cs0 unconnected. disconnects cs0 from all port pins, regardless of the selected channel. 0: cs0 connected to port pins 1: cs0 disconnected from port pins 6 reserved write = 0b 5:0 cs0mx[5:0] cs0 mux channel select. selects one of the 38 input channels for capacitive sense conversion. value 64-pin 48-pin 32-pin 24-pin value 64-pin 48-pin 32-pin 24-pin 000000 p2.0 p2.0 p2.0 p2.0 010011 p4.3 p4.3 ? p4.3 000001 p2.1 p2.1 p2.1 p2.1 010100 p4.4 ? ? p4.4 000010 p2.2 p2.2 p2.2 p2.2 010101 p4.5 ? ? p4.5 000011 p2.3 p2.3 p2.3 p2.3 010110 p4.6 ? ? p4.6 000100 p2.4 p2.4 p2.4 p2.4 010111 p4.7 ? ? p4.7 000101 p2.5 p2.5 p2.5 p2.5 011000 p5.0 p5.0 p5.0 ? 000110 p2.6 p2.6 p2.6 p2.6 011001 p5.1 p5.1 p5.1 ? 000111 p2.7 p2.7 p2.7 p2.7 011010 p5.2 p5.2 p5.2 ? 001000 p3.0 ? p3.0 ? 011011 p5.3 p5.3 p5.3 ? 001001 p3.1 ? p3.1 ? 011100 p5.4 p5.4 p5.4 ? 001010 p3.2 ? p3.2 ? 011101 p5.5 p5.5 p5.5 ? 001011 p3.3 ? p3.3 ? 011110 p5.6 p5.6 p5.6 ? 001100 p3.4 p3.4 p3.4 ? 011111 p5.7 p5.7 p5.7 ? 001101 p3.5 p3.5 p3.5 ? 100000 p6.0??? 001110 p3.6 p3.6 p3.6 ? 100001 p6.1??? 001111 p3.7 p3.7 ? ? 100010 p6.2??? 010000 p4.0 p4.0 ? p4.0 100011 p6.3 p6.3 p6.3 ? 010001 p4.1 p4.1 ? p4.1 100100 p6.4 p6.4 p6.4 p6.4 010010 p4.2 p4.2 ? p4.2 100101 p6.5 p6.5 p6.5 p6.5 c8051f70x/71x 98 rev. 1.0 16. cip-51 microcontroller the mcu system controller core is the cip-51 microcon troller. the cip-51 is fully compatible with the mcs-51? instruction set; standard 803x/805x assemble rs and compilers can be used to develop soft- ware. the mcu family has a superset of all the peri pherals included with a standard 8051. the cip-51 also includes on-chip debug hardware (see description in ?c2 interface? on page 301), and interfaces directly with the analog and digi tal subsystems providing a complete data acquisition or control-system solution in a single integrated circuit. the cip-51 microcontroller core implements the standard 8051 organization and peripherals as well as additional custom peripherals and functions to extend its capability (s ee figure 16.1 for a block diagram). the cip-51 includes the following features: performance the cip-51 employs a pipelined architecture that grea tly increases its instruction throughput over the stan- dard 8051 architecture. in a standar d 8051, all instructions except fo r mul and div take 12 or 24 system clock cycles to execute, and usually have a maximu m system clock of 12 mhz. by contrast, the cip-51 core executes 70% of its instructions in one or tw o system clock cycles, with no instructions taking more than eight system clock cycles. figure 16.1. cip-51 block diagram ?? fully compatible with mcs-51 instruction set ?? 25 mips peak throughput with 25 mhz clock ?? 0 to 25 mhz clock frequency ?? extended interrupt handler ?? reset input ?? power management modes ?? on-chip debug logic ?? program and data memory security data bus tmp1 tmp2 prgm. address reg. pc incrementer alu psw data bus data bus memory interface mem_address d8 pipeline buffer data pointer interrupt interface system_irqs emulation_irq mem_control control logic a16 program counter (pc) stop clock reset idle power control register data bus sfr bus interface sfr_address sfr_control sfr_write_data sfr_read_data d8 d8 b register d8 d8 accumulator d8 d8 d8 d8 d8 d8 d8 d8 mem_write_data mem_read_data d8 sram address register sram d8 stack pointer d8 rev. 1.0 99 c8051f70x/71x with the cip-51's maximum system clock at 25 mhz, it has a peak throughput of 25 mips. the cip-51 has a total of 109 instructions. the table below shows the to tal number of instructions that require each execu- tion time. 16.1. instruction set the instruction set of the cip-51 system controller is fully compatible with the standard mcs-51? instruc- tion set. standard 8051 development tools can be used to develop software for the cip-51. all cip-51 instructions are the binary and fu nctional equivalent of their mcs-51? counterparts, including opcodes, addressing modes and effect on psw flags. however, in struction timing is different than that of the stan- dard 8051. 16.1.1. instruction and cpu timing in many 8051 implementations, a distinction is ma de between machine cycles and clock cycles, with machine cycles varying from 2 to 12 clock cycles in length. however, the cip-51 implementation is based solely on clock cycle timing. all instructio n timings are specified in terms of clock cycles. due to the pipelined architecture of the cip-51, most instructions execute in the same number of clock cycles as there are program bytes in the instruction. conditional branch instruct ions take one less clock cycle to complete when the branch is not taken as o pposed to when the branch is taken. table 16.1 is the cip-51 instruction set summary, which includes the mnemonic, number of byte s, and number of clock cycles for each instruction. clocks to execute 1 22/333/444/55 8 number of instructions 26 50 5 14 7 3 1 2 1 c8051f70x/71x 100 rev. 1.0 table 16.1. cip-51 instruction set summary mnemonic description bytes clock cycles arithmetic operations add a, rn add register to a 1 1 add a, direct add direct byte to a 2 2 add a, @ri add indirect ram to a 1 2 add a, #data add immediate to a 2 2 addc a, rn add register to a with carry 1 1 addc a, direct add direct byte to a with carry 2 2 addc a, @ri add indirect ram to a with carry 1 2 addc a, #data add immediate to a with carry 2 2 subb a, rn subtract register from a with borrow 1 1 subb a, direct subtract direct byte from a with borrow 2 2 subb a, @ri subtract indirect ram from a with borrow 1 2 subb a, #data subtract imme diate from a with borrow 2 2 inc a increment a 1 1 inc rn increment register 1 1 inc direct increment direct byte 2 2 inc @ri increment indirect ram 1 2 dec a decrement a 1 1 dec rn decrement register 1 1 dec direct decrement direct byte 2 2 dec @ri decrement indirect ram 1 2 inc dptr increment data pointer 1 1 mul ab multiply a and b 1 4 div ab divide a by b 1 8 da a decimal adjust a 1 1 logical operations anl a, rn and register to a 1 1 anl a, direct and direct byte to a 2 2 anl a, @ri and indirect ram to a 1 2 anl a, #data and immediate to a 2 2 anl direct, a and a to direct byte 2 2 anl direct, #data and immediate to direct byte 3 3 orl a, rn or register to a 1 1 orl a, direct or direct byte to a 2 2 orl a, @ri or indirect ram to a 1 2 orl a, #data or immediate to a 2 2 orl direct, a or a to direct byte 2 2 orl direct, #data or immediate to direct byte 3 3 xrl a, rn exclusive-or register to a 1 1 xrl a, direct exclusive-or direct byte to a 2 2 xrl a, @ri exclusive-or indirect ram to a 1 2 xrl a, #data exclusive-or immediate to a 2 2 xrl direct, a exclusive-or a to direct byte 2 2 rev. 1.0 101 c8051f70x/71x xrl direct, #data exclusive-or immediate to direct byte 3 3 clr a clear a 1 1 cpl a complement a 1 1 rl a rotate a left 1 1 rlc a rotate a left through carry 1 1 rr a rotate a right 1 1 rrc a rotate a right through carry 1 1 swap a swap nibbles of a 1 1 data transfer mov a, rn move register to a 1 1 mov a, direct move direct byte to a 2 2 mov a, @ri move indirect ram to a 1 2 mov a, #data move immediate to a 2 2 mov rn, a move a to register 1 1 mov rn, direct move direct byte to register 2 2 mov rn, #data move immediate to register 2 2 mov direct, a move a to direct byte 2 2 mov direct, rn move register to direct byte 2 2 mov direct, direct move direct byte to direct byte 3 3 mov direct, @ri move indirect ram to direct byte 2 2 mov direct, #data move immediate to direct byte 3 3 mov @ri, a move a to indirect ram 1 2 mov @ri, direct move direct byte to indirect ram 2 2 mov @ri, #data move immediate to indirect ram 2 2 mov dptr, #data16 load dptr with 16-bit constant 3 3 movc a, @a+dptr move code byte relative dptr to a 1 3 movc a, @a+pc move code byte relative pc to a 1 3 movx a, @ri move external data (8-bit address) to a 1 3 movx @ri, a move a to external data (8-bit address) 1 3 movx a, @dptr move external data (16-bit address) to a 1 3 movx @dptr, a move a to external data (16-bit address) 1 3 push direct push direct byte onto stack 2 2 pop direct pop direct byte from stack 2 2 xch a, rn exchange register with a 1 1 xch a, direct exchange direct byte with a 2 2 xch a, @ri exchange indirect ram with a 1 2 xchd a, @ri exchange low nibble of indirect ram with a 1 2 boolean manipulation clr c clear carry 1 1 clr bit clear direct bit 2 2 setb c set carry 1 1 setb bit set direct bit 2 2 cpl c complement carry 1 1 cpl bit complement direct bit 2 2 table 16.1. cip-51 instruction set summary (continued) mnemonic description bytes clock cycles c8051f70x/71x 102 rev. 1.0 anl c, bit and direct bit to carry 2 2 anl c, /bit and complement of direct bit to carry 2 2 orl c, bit or direct bit to carry 2 2 orl c, /bit or complement of direct bit to carry 2 2 mov c, bit move direct bit to carry 2 2 mov bit, c move carry to direct bit 2 2 jc rel jump if carry is set 2 2/3 jnc rel jump if carry is not set 2 2/3 jb bit, rel jump if direct bit is set 3 3/4 jnb bit, rel jump if direct bit is not set 3 3/4 jbc bit, rel jump if direct bit is set and clear bit 3 3/4 program branching acall addr11 absolute subroutine call 2 3 lcall addr16 long subroutine call 3 4 ret return from subroutine 1 5 reti return from interrupt 1 5 ajmp addr11 absolute jump 2 3 ljmp addr16 long jump 3 4 sjmp rel short jump (relative address) 2 3 jmp @a+dptr jump indirect relative to dptr 1 3 jz rel jump if a equals zero 2 2/3 jnz rel jump if a does not equal zero 2 2/3 cjne a, direct, rel compare direct byte to a and jump if not equal 3 4/5 cjne a, #data, rel compare immediate to a and jump if not equal 3 3/4 cjne rn, #data, rel compare immediate to register and jump if not equal 33/4 cjne @ri, #data, rel compare immediate to indirect and jump if not equal 34/5 djnz rn, rel decrement regist er and jump if not zero 2 2/3 djnz direct, rel decrement direct byte and jump if not zero 3 3/4 nop no operation 1 1 table 16.1. cip-51 instruction set summary (continued) mnemonic description bytes clock cycles rev. 1.0 103 c8051f70x/71x notes on registers, operands and addressing modes: rn ?register r0?r7 of the currently selected register bank. @ri ?data ram location addressed indirectly through r0 or r1. rel ?8-bit, signed (twos complement) offset relative to the first byte of the follo wing instruction. used by sjmp and all conditional jumps. direct ?8-bit internal data location?s address. this could be a direct-access data ram location (0x00? 0x7f) or an sfr (0x80?0xff). #data ?8-bit constant #data16 ?16-bit constant bit ?direct-accessed bit in data ram or sfr addr11 ?11-bit destination address used by acall a nd ajmp. the destination must be within the same 2 kb page of program memory as the first byte of the following instruction. addr16 ?16-bit destination address used by lcall and ljmp. the destination may be anywhere within the 8 kb program memory space. there is one unused opcode (0xa5) that performs the same function as nop. all mnemonics copyrighted ? intel corporation 1980. c8051f70x/71x 104 rev. 1.0 16.2. cip-51 re gister descriptions following are descriptions of sfrs related to the opera tion of the cip-51 system controller. reserved bits should always be written to the value indicated in the sfr description. future product versions may use these bits to implem ent new features in which ca se the reset value of the bi t will be the indicated value, selecting the feature's default state. detailed descriptions of the remaining sfrs are included in the sec- tions of the data sheet associated wit h their corresponding system function. sfr address = 0x82; sfr page = all pages sfr address = 0x83; sfr page = all pages sfr definition 16.1. dpl: data pointer low byte bit76543210 name dpl[7:0] type r/w reset 00000000 bit name function 7:0 dpl[7:0] data pointer low. the dpl register is the low byte of the 16-bit dptr. sfr definition 16.2. dph: data pointer high byte bit76543210 name dph[7:0] type r/w reset 00000000 bit name function 7:0 dph[7:0] data pointer high. the dph register is the high byte of the 16-bit dptr. rev. 1.0 105 c8051f70x/71x sfr address = 0x81; sfr page = all pages sfr address = 0xe0; sfr page = all pages; bi t-addressable sfr definition 16.3. sp: stack pointer bit76543210 name sp[7:0] type r/w reset 00000111 bit name function 7:0 sp[7:0] stack pointer. the stack pointer holds the location of the to p of the stack. the stack pointer is incre- mented before every push operation. the sp register defaults to 0x07 after reset. sfr definition 16.4. acc: accumulator bit76543210 name acc[7:0] type r/w reset 00000000 bit name function 7:0 acc[7:0] accumulator. this register is the accumulator for arithmetic operations. c8051f70x/71x 106 rev. 1.0 sfr address = 0xf0; sfr page = all pages; bit-addressable sfr definition 16.5. b: b register bit76543210 name b[7:0] type r/w reset 00000000 bit name function 7:0 b[7:0] b register. this register serves as a second accumu lator for certain arithmetic operations. rev. 1.0 107 c8051f70x/71x sfr address = 0xd0; sfr page = all pages; bit-addressable sfr definition 16.6. psw: program status word bit76543210 name cy ac f0 rs[1:0] ov f1 parity type r/w r/w r/w r/w r/w r/w r reset 00000000 bit name function 7cy carry flag. this bit is set when the last arithmetic oper ation resulted in a carry (addition) or a bor- row (subtraction). it is cleared to logi c 0 by all other arithmetic operations. 6ac auxiliary carry flag. this bit is set when the last arithmetic operat ion resulted in a carry into (addition) or a borrow from (subtraction) the high order nibble. it is cleared to logic 0 by all other arith- metic operations. 5f0 user flag 0. this is a bit-addressable, general purp ose flag for use under software control. 4:3 rs[1:0] register bank select. these bits select which register bank is used during register accesses. 00: bank 0, addresses 0x00-0x07 01: bank 1, addresses 0x08-0x0f 10: bank 2, addresses 0x10-0x17 11: bank 3, addresses 0x18-0x1f 2ov overflow flag. this bit is set to 1 under the following circumstances: ?? an add, addc, or subb instruction causes a sign-change overflow. ?? a mul instruction results in an overflow (result is greater than 255). ?? a div instruction causes a divide-by-zero condition. the ov bit is cleared to 0 by the add, a ddc, subb, mul, and div instructions in all other cases. 1f1 user flag 1. this is a bit-addressable, general purp ose flag for use under software control. 0parity parity flag. this bit is set to logic 1 if the sum of the ei ght bits in the accumulator is odd and cleared if the sum is even. c8051f70x/71x 108 rev. 1.0 17. memory organization the memory organization of the cip-51 system controller is similar to that of a standard 8051. there are two separate memory spaces: program memory and data memory. program and data memory share the same address space but are accessed via different instruction types. the memory organization of the c8051f70x/71x device family is shown in figure 17.1 figure 17.1. c8051f70x/71x memory map program/data memory (flash) (direct and indirect addressing) 0x00 0x7f upper 128 ram (indirect addressing only) 0x80 0xff special function register's (direct addressing only) data memory (ram) general purpose registers 0x1f 0x20 0x2f bit addressable lower 128 ram (direct and indirect addressing) 0x30 internal data address space external data address space xram - 256 bytes (accessable using movx instruction) 0x0000 0x00ff same 256 bytes as from 0x0000 to 0x01ff, wrapped on 256-byte boundaries 0x0100 0xffff 16 k bytes flash (in-system programmable in 512 byte sectors) 0x0000 lock byte 0x3fff 0x3ffe c8051f702/3/6/7 and c8051f716/7 15 k bytes flash (in-system programmable in 512 byte sectors) 0x0000 lock byte 0x3bff 0x3bfe c8051f700/1/4/5 8 k bytes flash (in-system programmable in 512 byte sectors) 0x0000 lock byte 0x1fff 0x1ffe c8051f708/9 and c8051f710/1/2/3/4/5 rev. 1.0 109 c8051f70x/71x 17.1. program memory the members of the c8051f70x/71x device family contain 16 kb (c8051f702/3/6/7 and c8051f16/7), 15 kb (c8051f700/1/4/5), or 8 kb (c8051f708/9 and c8051f710/1/2/3/4/5) of re-programmable flash memory that can be used as non-volatile program or data storage. the last by te of user code space is used as the security lock byte (0x3fff on 16 kb devices, 0x3bff on 15 kb devices and 0x1fff on 8 kb devices). figure 17.2. flash program memory map 17.1.1. movx instructio n and program memory the movx instruction in an 8051 device is typica lly used to access external data memory. on the c8051f70x/71x devices, the movx instruction is norma lly used to read and write on-chip xram, but can be re-configured to write and erase on-chip flash me mory space. movc instructions are always used to read flash memory, while movx write instructions are used to erase an d write flash. this flash access feature provides a mechanism for the c8051f70x/71x to update program code and use the program mem- ory space for non-volatile data storage. refer to section ?22. flash memory? on page 148 for further details. 17.2. eeprom memory the c8051f700/1/4/5/8/9 and c805 1f712/3 contain eeprom emulation hardware, which uses flash memory to emulate a 32-b yte eeprom memory space for non-volat ile data storage. the eeprom data is accessed through a ram buffer for increased speed. mo re details about the eeprom can be found in section ?23. eeprom? on page 155. 17.3. data memory the c8051f70x/71x device family includes 512 byte s of ram data memory. 256 bytes of this memory is mapped into the internal ram space of the 8051. 256 bytes of this memory is on-chip ?external? memory. the data memory map is shown in figure 17.1 for reference. 17.3.1. internal ram there are 256 bytes of internal ram mapped into the data memory space from 0x00 through 0xff. the lower 128 bytes of data memory are used for genera l purpose registers and scratch pad memory. either direct or indirect addressing may be used to access the lower 128 bytes of data memory. locations 0x00 through 0x1f are addressable as four banks of gene ral purpose registers, each bank consisting of eight lock byte 0x0000 0x3fff 0x3ffe flash memory organized in 512-byte pages 0x3e00 flash memory space lock byte page lock byte 0x0000 0x3bff 0x3bfe 0x3a00 flash memory space lock byte page lock byte 0x0000 0x1fff 0x1ffe 0x1e00 flash memory space lock byte page c8051f702/3/6/7 and c8051f716/7 c8051f700/1/4/5 c8051f708/9 and c8051f710/1/2/3/4/5 c8051f70x/71x 110 rev. 1.0 byte-wide registers. the next 16 bytes, locations 0x 20 through 0x2f, may either be addressed as bytes or as 128 bit locations accessible with the direct addressing mode. the upper 128 bytes of data memory are accessible only by indirect addressing. this region occupies the same address space as the special function regist ers (sfr) but is physically separate from the sfr space. the addressing mode used by an instructio n when accessing locations above 0x7f determines whether the cpu accesses the upper 128 bytes of data memory space or the sfrs. instructions that use direct addressing will access the sfr space. instructions using indirect addressing above 0x7f access the upper 128 bytes of data memory. figure 17.1 illustrates the data memory organization of the c8051f70x/71x. 17.3.1.1. general purpose registers the lower 32 bytes of data memory, locations 0x00 through 0x1f, may be addressed as four banks of gen- eral-purpose registers. each bank consists of ei ght byte-wide registers designated r0 through r7. only one of these banks may be enabled at a time. two bi ts in the program status word, rs0 (psw.3) and rs1 (psw.4), select the active register bank (see desc ription of the psw in sfr definition 16.6). this allows fast context switching when entering subroutines and in terrupt service routines. in direct addressing modes use registers r0 and r1 as index registers. 17.3.1.2. bit addressable locations in addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20 through 0x2f are also accessible as 128 individually addressable bits. each bit has a bit address from 0x00 to 0x7f. bit 0 of the byte at 0x20 has bit address 0x00 while bit7 of the byte at 0x20 has bit address 0x07. bit 7 of the byte at 0x2f has bit address 0x7f. a bit access is distinguished from a full byte access by the type of instruction used (bit source or destinat ion operands as opposed to a byte source or destina- tion). the mcs-51? assembly language allows an alternate notation for bit addressing of the form xx.b where xx is the byte address and b is the bit position within the byte. for example, the instruction: mov c, 22.3h moves the boolean value at 0x13 (bit 3 of the byte at location 0x22) into the carry flag. 17.3.1.3. stack a programmer's stack can be located anywhere in the 256-byte data memory. the stack area is desig- nated using the stack pointer (sp) sfr. the sp will point to the last lo cation used. the next value pushed on the stack is placed at sp+1 and then sp is incremen ted. a reset initializes t he stack pointer to location 0x07. therefore, the first value pushed on the stack is placed at location 0x08, which is also the first regis- ter (r0) of register bank 1. thus, if more than one register bank is to be used, the sp should be initialized to a location in the data memory not being used for data storage. the stack depth can extend up to 256 bytes. rev. 1.0 111 c8051f70x/71x 18. external data memory interface and on-chip xram for c8051f70x/71x devices, 256 b of ram are included on-chip and mapped into the external data mem- ory space (xram). additionally, an external memory interface (emif) is available on the c8051f700/1/2/3/8/9 and c8051f710/1 devices, which c an be used to access off-chip data memories and memory-mapped devices connected to the gpio port s. the external memory space may be accessed using the external move instruction (movx) and the data pointer (dptr), or using the movx indirect addressing mode using r0 or r1. if the movx inst ruction is used with an 8-bit address operand (such as @r1), then the high byte of the 16-bit address is pr ovided by the external memory interface control reg- ister (emi0cn, shown in sfr definition 18.1). note: the movx instruction can also be used for writing to the flash memory. see section ? 22. flash memory ? on page 148 for details. the movx instru ction accesses xram by default. 18.1. accessing xram the xram memory space is accessed using the mo vx instruction. the movx instruction has two forms, both of which use an indirect addressing method. th e first method uses the data pointer, dptr, a 16-bit register which contains the effective address of the xram location to be read from or written to. the sec- ond method uses r0 or r1 in combination with th e emi0cn register to generate the effective xram address. examples of both of these methods are given below. 18.1.1. 16-bit movx example the 16-bit form of the movx instruction accesses the memory location pointed to by the contents of the dptr register. the following series of instructions reads the value of the byte at address 0x1234 into the accumulator a: mov dptr, #1234h ; load dptr with 16-bit address to read (0x1234) movx a, @dptr ; load contents of 0x1234 into accumulator a the above example uses the 16-bit immediate mov in struction to set the contents of dptr. alternately, the dptr can be accessed through the sfr registers dph, which contains the upper 8-bits of dptr, and dpl, which contains the lower 8-bits of dptr. 18.1.2. 8-bit movx example the 8-bit form of the movx instruction uses the cont ents of the emi0cn sfr to determine the upper 8-bits of the effective address to be accessed and the contents of r0 or r1 to determine the lower 8-bits of the effective address to be accessed. the following series of instructions read the contents of the byte at address 0x1234 into the accumulator a. mov emi0cn, #12h ; load high byte of address into emi0cn mov r0, #34h ; load low byte of address into r0 (or r1) movx a, @r0 ; load contents of 0x1234 into accumulator a c8051f70x/71x 112 rev. 1.0 18.2. configuring the ex ternal memory interface configuring the external memory interface consists of five steps: 1. configure the output modes of the associated port pi ns as either push-pull or open-drain (push-pull is most common). 2. configure port latches to ?park? the emif pins in a dormant state (usually by setting them to logic 1). 3. select multiplexed mode or non-multiplexed mode. 4. select the memory mode (on-chip only, split mode without bank select, split mode with bank select, or off-chip only). 5. set up timing to interface with off-chip memory or peripherals. each of these five steps is explained in detail in the following sections. the po rt selection, multiplexed mode selection, and mode bits are located in the emi0cf register shown in sfr definition . 18.3. port configuration the emif pinout is shown in figure 18.2 on page 127 the external memory interface claims the associated port pins for memory oper ations only during the execution of an off-chip movx instruction. once the movx instruction has completed, control of the port pins reverts to the port latches for those pins. se e section ?28. port input/output? on page 180 for more information about port operation and configuration. the port latches should be explicitly configured to ?park? the external memory interface pins in a dormant state, most commonly by setting them to a logic 1. during the execution of the movx instruction, the external memory interf ace will explicitly disable the driv- ers on all port pins that are acting as inputs (dat a[7:0] during a read operati on, for example). the output mode of the port pins (whether the pin is configured as open-drain or push-pull) is unaffected by the external memory interface operation, and remains c ontrolled by the pnmdout registers. in most cases, the output modes of all emif pins should be configured for push-pull mode. rev. 1.0 113 c8051f70x/71x sfr address = 0xaa; sfr page = f sfr definition 18.1. emi0cn: exte rnal memory interface control bit76543210 name pgsel[7:0] type r/w reset 00000000 bit name function 7:0 pgsel[7:0] xram page select bits. the xram page select bits provide the high byte of the 16-bit external data memory address when using an 8-bit movx command, ef fectively selecting a 256-byte page of ram. 0x00: 0x0000 to 0x00ff 0x01: 0x0100 to 0x01ff ... 0xfe: 0xfe00 to 0xfeff 0xff: 0xff00 to 0xffff c8051f70x/71x 114 rev. 1.0 sfr address = 0xc7; sfr page = f sfr definition 18.2. emi0cf: ex ternal memory configuration bit76543210 name emd2 emd[1:0] eale[1:0] type rr/w reset 00000011 bit name function 7:5 unused read = 000b; write = don?t care. 4emd2 emif multiplex mode select bit. 0: emif operates in mult iplexed address/data mode 1: emif operates in non-multiplexed mode (separate address and data pins) 3:2 emd[1:0] emif operating m ode select bits. 00: internal only: movx accesses on-chip xram only. all effective addresses alias to on-chip memory space 01: split mode without bank select: acce sses below the 256 b boundary are directed on-chip. accesses above the 256 b boundary are directed off-chip. 8-bit off-chip movx operations use current contents of the addres s high port latches to resolve the upper address byte. to access off chip space, emi0 cn must be set to a page that is not con- tained in the on-chip address space. 10: split mode with bank select: accesses below the 256 b boundary are directed on- chip. accesses above the 256 b boundary are directed off-chip. 8-bit off-chip movx operations uses the contents of emi0cn to determine the high-byte of the address. 11: external only: movx access es off-chip xram only. on-chip xram is not visible to the cpu. 1:0 eale[1:0] ale pulse-width select bits. these bits only have an effect when emd2 = 0. 00: ale high and ale low pu lse width = 1 sysclk cycle. 01: ale high and ale low pu lse width = 2 sysclk cycles. 10: ale high and ale low pu lse width = 3 sysclk cycles. 11: ale high and ale low pulse width = 4 sysclk cycles. rev. 1.0 115 c8051f70x/71x 18.4. multiplexed and n on-multiplexed selection the external memory interface is capable of acting in a multiplexe d mode or a non-multiplexed mode, depending on the state of the emd2 (emi0cf.4) bit. 18.4.1. mult iplexed configuration in multiplexed mode, the data bus and the lower 8-bits of the address bus share the same port pins: ad[7:0]. in this mode , an external latch (74hc373 or equivalent logic gate) is used to hold the lower 8-bits of the ram address. the external latch is controlle d by the ale (address latch enable) signal, which is driven by the external memory interface logic. an example of a multiplexed configuration is shown in figure 18.1. in multiplexed mode, the external movx operation can be broken into two phases delineated by the state of the ale signal. during the first phase, ale is high and the lower 8-bits of the address bus are pre- sented to ad[7:0]. during this phase, the address latc h is configured such that the q outputs reflect the states of the ?d? inputs. when ale falls, signaling th e beginning of the second phase, the address latch outputs remain fixed and are no longer dependent on the latch inputs. later in the second phase, the data bus controls the state of the ad[7:0] port at the time rd or wr is asserted. see section ?18.6.2. multiplexed mode? on page 123 for more information. figure 18.1. multiplexed configuration example address/data bus address bus e m i f a[15:8] ad[7:0] wr rd ale 64 k x 8 sram oe we i/o[7:0] 74hc373 g dq a[15:8] a[7:0] ce v dd 8 (optional) c8051f70x/71x 116 rev. 1.0 18.4.2. non-multiple xed configuration in non-multiplexed mode, the data bus and the addr ess bus pins are not shared. an example of a non- multiplexed configuration is shown in figure 18.2. see section ?18.6.1. non-multiplexed mode? on page 120 for more information about non-multiplexed operation. figure 18.2. non-multiplexed configuration example address bus e m i f a[15:0] 64 k x 8 sram a[15:0] data bus d[7:0] i/o[7:0] v dd 8 wr rd oe we ce (optional) rev. 1.0 117 c8051f70x/71x 18.5. memory mode selection the external data memory space can be configured in one of four modes, shown in figure 18.3, based on the emif mode bits in the emi0cf register (sfr definition 18.2). these modes are summarized below. more information about the different modes can be found in section ?18.6. timing? on page 118. figure 18.3. emif operating modes 18.5.1. intern al xram only when bits emi0cf[3:2] are set to 00, all movx instructions will target the internal xram space on the device. memory accesses to addresses beyond the populated space will wrap on 4 kb boundaries. as an example, the addresses 0x1000 and 0x2000 both evaluate to address 0x0000 in on-chip xram space. ? 8-bit movx operations use the contents of emi0cn to determine the high-byte of the effective address and r0 or r1 to determine the lo w-byte of the effective address. ? 16-bit movx operations use the contents of the 16-bit dptr to determine the effective address. 18.5.2. split mode without bank select when bit emi0cf.[3:2] are set to 01, the xram memory map is split into two areas, on-chip space and off- chip space. ? effective addresses below the in ternal xram size boundary will access on-chip xram space. ? effective addresses above the internal xram size boundary will access off-chip space. ? 8-bit movx operations use the contents of emi0 cn to determine whether the memory access is on- chip or off-chip. however, in th e ?no bank select? mode, an 8-bi t movx operation will not drive the upper 8-bits a[15:8] of the address bus during an off-chip access. this allows the user to manipulate the upper address bits at will by setting the port state directly via the port latc hes. this behavior is in contrast with ?split mode with bank select? described below. the lower 8-bits of the address bus a[7:0] are driven, determined by r0 or r1. ? 16-bit movx operations use the contents of dptr to determine whether the memory access is on-chip or off-chip, and unlike 8-bit movx operations, the full 16-bits of the address bus a[15:0] are driven during the off-chip transaction. emi0cf[3:2] = 00 0xffff 0x0000 emi0cf[3:2] = 11 0xffff 0x0000 emi0cf[3:2] = 01 0xffff 0x0000 emi0cf[3:2] = 10 on-chip xram on-chip xram on-chip xram on-chip xram on-chip xram on-chip xram off-chip memory (no bank select) on-chip xram 0xffff 0x0000 off-chip memory (bank select) on-chip xram off-chip memory c8051f70x/71x 118 rev. 1.0 18.5.3. split mode with bank select when emi0cf[3:2] are set to 10, the xram memory map is split into two areas, on-chip space and off- chip space. ? effective addresses below the in ternal xram size boundary will access on-chip xram space. ? effective addresses above the internal xram size boundary will access off-chip space. ? 8-bit movx operations use the contents of emi0 cn to determine whether the memory access is on- chip or off-chip. the upper 8-bits of the address bus a[15:8] are determined by emi0cn, and the lower 8-bits of the address bus a[7:0] are determined by r0 or r1. all 16-bits of the address bus a[15:0] are driven in ?bank select? mode. ? 16-bit movx operations use the contents of dptr to determine whether the memory access is on-chip or off-chip, and the full 16-bits of the address bus a[15:0] are driven during the off-chip transaction. 18.5.4. external only when emi0cf[3:2] are set to 11, all movx operations ar e directed to off-chip space. on-chip xram is not visible to the cpu. this mode is useful for accessing off-chip memo ry located between 0x0000 and the internal xram size boundary. ? 8-bit movx operations ignore the contents of emi0 cn. the upper address bits a[15:8] are not driven (identical behavior to an off-chip access in ?split mode without bank select? described above). this allows the user to manipulate the up per address bits at will by setting the port state directly. the lower 8-bits of the effective address a[7:0] are determined by the contents of r0 or r1. ? 16-bit movx operations use the contents of dptr to determine the effective address a[15:0]. the full 16-bits of the address bus a[15:0] are driven during the off-chip transaction. 18.6. timing the timing parameters of the external memory in terface can be configured to enable connection to devices having different setup and hold time requirements. the address setup time, address hold time, rd and wr strobe widths, and in multip lexed mode, the width of the ale pulse are all programmable in units of sysclk periods throug h emi0tc, shown in sfr defini tion 18.3, and emi0cf[1:0]. the timing for an off-chip movx instruction can be calculated by adding 4 sysclk cycles to the timing parameters defined by the emi0tc register. assumi ng non-multiplexed operation, the minimum execution time for an off-chip xram operatio n is 5 sysclk cycles (1 sysclk for rd or wr pulse + 4 sysclks). for multiplexed operations , the address latch enable signal will re quire a minimum of 2 additional sys- clk cycles. therefore, the minimum ex ecution time for an off-chip xram operation in multiplexed mode is 7 sysclk cycles (2 for /ale + 1 for rd or wr + 4). the programmable setup and hold times default to the maximum delay settings after a reset. table 18.1 lists the ac parameters for the external memory inter- face, and figure 18.4 through figure 18.9 show the ti ming diagrams for the different external memory interface modes and movx operations. rev. 1.0 119 c8051f70x/71x sfr address = 0xee; sfr page = f sfr definition 18.3. emi0tc: ex ternal memory timing control bit76543210 name eas[1:0] ewr[3:0] eah[1:0] type r/w r/w r/w reset 11111111 bit name function 7:6 eas[1:0] emif address setup time bits. 00: address setup time = 0 sysclk cycles. 01: address setup time = 1 sysclk cycle. 10: address setup time = 2 sysclk cycles. 11: address setup time = 3 sysclk cycles. 5:2 ewr[3:0] emif wr and rd pulse-width control bits. 0000: wr and rd pulse width = 1 sysclk cycle. 0001: wr and rd pulse width = 2 sysclk cycles. 0010: wr and rd pulse width = 3 sysclk cycles. 0011: wr and rd pulse width = 4 sysclk cycles. 0100: wr and rd pulse width = 5 sysclk cycles. 0101: wr and rd pulse width = 6 sysclk cycles. 0110: wr and rd pulse width = 7 sysclk cycles. 0111: wr and rd pulse width = 8 sysclk cycles. 1000: wr and rd pulse width = 9 sysclk cycles. 1001: wr and rd pulse width = 10 sysclk cycles. 1010: wr and rd pulse width = 11 sysclk cycles. 1011: wr and rd pulse width = 12 sysclk cycles. 1100: wr and rd pulse width = 13 sysclk cycles. 1101: wr and rd pulse width = 14 sysclk cycles. 1110: wr and rd pulse width = 15 sysclk cycles. 1111: wr and rd pulse width = 16 sysclk cycles. 1:0 eah[1:0] emif address hold time bits. 00: address hold time = 0 sysclk cycles. 01: address hold time = 1 sysclk cycle. 10: address hold time = 2 sysclk cycles. 11: address hold time = 3 sysclk cycles. c8051f70x/71x 120 rev. 1.0 18.6.1. non-multiplexed mode 18.6.1.1. 16-bit movx: emi0 cf[4:2] = 101, 110, or 111 figure 18.4. non-multiplexed 16-bit movx timing emif address (8 msbs) from dph emif address (8 lsbs) from dpl emif write data t ach t wdh t acw t acs t wds addr[15:8] addr[7:0] data[7:0] wr rd emif address (8 msbs) from dph emif address (8 lsbs) from dpl t ach t rdh t acw t acs t rds addr[15:8] addr[7:0] data[7:0] rd wr emif read data nonmuxed 16-bit write nonmuxed 16-bit read rev. 1.0 121 c8051f70x/71x 18.6.1.2. 8-bit movx without bank select: emi0cf[4:2] = 101 or 111 figure 18.5. non-multiplexed 8-bit movx without bank select timing emif address (8 lsbs) from r0 or r1 emif write data t ach t wdh t acw t acs t wds addr[15:8] addr[7:0] data[7:0] wr rd emif address (8 lsbs) from r0 or r1 t ach t rdh t acw t acs t rds addr[15:8] addr[7:0] data[7:0] rd wr emif read data nonmuxed 8-bit write without bank select nonmuxed 8-bit read without bank select c8051f70x/71x 122 rev. 1.0 18.6.1.3. 8-bit mo vx with bank select: emi0cf[4:2] = 110 figure 18.6. non-multiplexed 8-bit movx with bank select timing emif address (8 msbs) from emi0cn emif address (8 lsbs) from r0 or r1 emif write data t ach t wdh t acw t acs t wds addr[15:8] addr[7:0] data[7:0] wr rd emif address (8 msbs) from emi0cn emif address (8 lsbs) from r0 or r1 t ach t rdh t acw t acs t rds addr[15:8] addr[7:0] data[7:0] rd wr emif read data nonmuxed 8-bit write with bank select nonmuxed 8-bit read with bank select rev. 1.0 123 c8051f70x/71x 18.6.2. mult iplexed mode 18.6.2.1. 16-bit movx: emi0 cf[4:2] = 001, 010, or 011 figure 18.7. multiplexed 16-bit movx timing addr[15:8] ad[7:0] t ach t wdh t acw t acs t wds ale wr rd emif address (8 msbs) from dph emif write data emif address (8 lsbs) from dpl t aleh t alel addr[15:8] ad[7:0] t ach t acw t acs ale rd wr emif address (8 msbs) from dph emif address (8 lsbs) from dpl t aleh t alel t rdh t rds emif read data muxed 16-bit write muxed 16-bit read c8051f70x/71x 124 rev. 1.0 18.6.2.2. 8-bit movx without bank select: emi0cf[4:2] = 001 or 011 figure 18.8. multiplexed 8-bit movx without bank select timing addr[15:8] ad[7:0] t ach t wdh t acw t acs t wds ale wr rd emif write data emif address (8 lsbs) from r0 or r1 t aleh t alel addr[15:8] ad[7:0] t ach t acw t acs ale rd wr emif address (8 lsbs) from r0 or r1 t aleh t alel t rdh t rds emif read data muxed 8-bit write without bank select muxed 8-bit read without bank select l rev. 1.0 125 c8051f70x/71x 18.6.2.3. 8-bit mo vx with bank select: emi0cf[4:2] = 010 figure 18.9. multiplexed 8-bit movx with bank select timing addr[15:8] ad[7:0] t ach t wdh t acw t acs t wds ale wr rd emif address (8 msbs) from emi0cn emif write data emif address (8 lsbs) from r0 or r1 t aleh t alel addr[15:8] ad[7:0] t ach t acw t acs ale rd wr emif address (8 msbs) from emi0cn emif address (8 lsbs) from r0 or r1 t aleh t alel t rdh t rds emif read data muxed 8-bit write with bank select muxed 8-bit read with bank select c8051f70x/71x 126 rev. 1.0 table 18.1. ac parameters for external memory interface parameter description min* max* units t acs address/control setup time 0 3 x t sysclk ns t acw address/control pulse width t sysclk 16 x t sysclk ns t ach address/control hold time 0 3 x t sysclk ns t aleh address latch enable high time t sysclk 4 x t sysclk ns t alel address latch enable low time t sysclk 4 x t sysclk ns t wds write data setup time t sysclk 19 x t sysclk ns t wdh write data hold time 0 3 x t sysclk ns t rds read data setup time 20 ? ns t rdh read data hold time 0 ? ns note: t sysclk is equal to one period of the device system clock (sysclk). rev. 1.0 127 c8051f70x/71x table 18.2. emif pinout (c8051f700/1/2/3/8/9 and c8051f710/1) multiplexed mode non multiplexed mode signal name port pin signal name port pin rd p6.1 rd p6.1 wr p6.0 wr p6.0 ale p6.2 d0 p5.0 d0/a0 p5.0 d1 p5.1 d1/a1 p5.1 d2 p5.2 d2/a2 p5.2 d3 p5.3 d3/a3 p5.3 d4 p5.4 d4/a4 p5.4 d5 p5.5 d5/a5 p5.5 d6 p5.6 d6/a6 p5.6 d7 p5.7 d7/a7 p5.7 a0 p4.0 a8 p4.0 a1 p4.1 a9 p4.1 a2 p4.2 a10 p4.2 a3 p4.3 a11 p4.3 a4 p4.4 a12 p4.4 a5 p4.5 a13 p4.5 a6 p4.6 a14 p4.6 a7 p4.7 a15 p4.7 a8 p3.0 ? ? a9 p3.1 ?? a10p3.2 ?? a11p3.3 ?? a12p3.4 ?? a13p3.5 ?? a14p3.6 ?? a15p3.7 c8051f70x/71x 128 rev. 1.0 19. in-system device identification the c8051f70x/71x has sfrs that id entify the device family and derivat ive. these sfrs can be read by firmware at runtime to determine the capabilities of the mcu that is ex ecuting code. this allows the same firmware image to run on mcus with different memory sizes and peripherals, and dynamically changing functionality to suit the capabilities of that mcu. in order for firmware to identify the mcu, it must read three sfrs. hwid describes the mcu?s family, derivid describes the specific der ivative within that device family , and revid describes the hardware revision of the mcu. sfr address = 0xc4; sfr page = f sfr address = 0xec; sfr page = f sfr definition 19.1. hwid: ha rdware identification byte bit76543210 name hwid[7:0] type rrrrrrrr reset 00011110 bit name description 7:0 hwid[7:0] hardware identification byte. describes the mcu family. 0x1e: devices covered in this document (c8051f70x/71x) sfr definition 19.2. derivid: derivative iden tification byte bit76543210 name derivid[7:0] type rrrrrrrr reset varies varies varies varies varies varies varies varies bit name description 7:0 derivid[7:0] derivative identification byte. shows the c8051f70x/71x derivative being used. 0xd0: c8051f700; 0xd1: c8051f701; 0xd2: c8051f702; 0xd3: c8051f703 0xd4: c8051f704; 0xd5: c8051f705; 0xd6: c8051f706; 0xd7: c8051f707 0xd8: c8051f708; 0xd9: c8051f709; 0xda: c8051f710; 0xdb: c8051f711 0xdc: c8051f712; 0xdd: c8051f713; 0xde: c8051f714; 0xdf: c8051f715 0xe0: c8051f716; 0xe1: c8051f717 rev. 1.0 129 c8051f70x/71x sfr address = 0xad; sfr page = f sfr definition 19.3. revid: hardwa re revision iden tification byte bit76543210 name revid[7:0] type rrrrrrrr reset varies varies varies varies varies varies varies varies bit name description 7:0 revid[7:0] hardware revisi on identification byte. shows the c8051f70x/71x hardware revision being used. for example, 0x00 = revision a. c8051f70x/71x 130 rev. 1.0 20. special function registers the direct-access data memory locations from 0x80 to 0xff constitute the sp ecial function registers (sfrs). the sfrs provide control and data exchang e with the c8051f70x/71x's resources and peripher- als. the cip-51 controller core duplicates the sfrs found in a typical 8051 implementation as well as implementing additional sfrs used to config ure and access the sub-systems unique to the c8051f70x/71x. this allows the add ition of new functiona lity while retaining compatibility with the mcs- 51? instruction set. table 20.1 lists the sfrs implemented in the c8051f70x/71x device family. the sfr registers are accessed anytime the direct ad dressing mode is used to access memory locations from 0x80 to 0xff. sfrs with addresses ending in 0x0 or 0x8 (e.g., p0, tcon, scon0, ie, etc.) are bit- addressable as well as byte-addressable. all other sfrs are byte-addressable only. unoccupied addresses in the sfr space are reserved for future use. accessing t hese areas will have an indeterminate effect and should be avoided. refer to the corres ponding pages of the data sheet, as indicated in table 20.2, for a detailed description of each register. rev. 1.0 131 c8051f70x/71x table 20.1. special function register (sfr) memory map addr sfr page 0(8) 1(9) 2(a) 3(b) 4(c) 5(d) 6(e) 7(f) f8 0 f spi0cn pca0l p0drv pca0h p1drv pca0cpl0 p2drv pca0cph0 p3drv p4drv p5drv vdm0cn f0 0 f b p0mdin p1mdin p0mat p2mdin p0mask p3mdin p4mdin p5mdin p6mdin e8 0 f adc0cn pca0cpl1 pca0cph1 pca0cpl2 pca0cph2 derivid pca0md emi0tc rstsrc e0 0 f acc p1mat xbr0 p1mask xbr1 wdtcn it01cf eie1 eie2 d8 0 f pca0cn crc0data pca0cpm0 pca0cpm1 pca0cpm2 d0 0 f psw eedata ref0cn p0skip p1skip p2skip c8 0 f tmr2cn tmr2rll tmr2rlh tmr2l tmr2h eip1 eip2 c0 0 f smb0cn smb0cf p6drv smb0dat adc0gtl adc0gth hwid adc0ltl eecntl adc0lth eekey emi0cf b8 0 f ip reg0cn smb0adr adc0mx smb0adm adc0cf adc0l clksel adc0h cs0md2 oscicl b0 0 f p3 p6 p5 oscxcn eeaddr flkey a8 0 f ie cs0dl oscicn cs0dh emi0cn p4 cs0md1 revid p3mdout a0 0 f p2 spi0cfg pca0pwm spi0ckr spi0dat p0mdout p1mdout p2mdout sfrpage 98 0 f scon0 sbuf0 cs0cn p4mdout cpt0cn p5mdout cs0mx p6mdout cpt0md cs0cf cpt0mx cs0pm 90 0 f p1 tmr3cn crc0cn tmr3rll cs0ss tmr3rlh cs0se tmr3l crc0in tmr3h crc0flip cs0thl crc0auto cs0thh crc0cnt 88 0 f tcon tmod tl0 tl1 th0 th1 ckcon psctl 80 0 f p0 sp dpl dph pcon 0(8) 1(9) 2(a) 3(b) 4(c) 5(d) 6(e) 7(f) notes: 1. sfr addresses ending in 0x0 or 0x8 (leftmost column) are bit-addressable. 2. sfrs indicated with bold lettering and shaded cells are available on both sfr page 0 and f. c8051f70x/71x 132 rev. 1.0 sfr address = 0xa7; sfr page = all pages sfr definition 20.1. sfrpage: sfr page bit76543210 name sfrpage[7:0] type r/w reset 00000000 bit name description 7:0 sfrpage[7:0] sfr page bits. represents the sfr page the c8051 core uses when reading or modifying sfrs. write: sets the sfr page. read: byte is the sfr page the c8051 core is using. table 20.2. special function registers sfrs are listed in alphabetical order. all undefined sfr locations are reserved register address page description page acc 0xe0 all pages accumulator 105 adc0cf 0xbc f adc0 configuration 59 adc0cn 0xe8 all pages adc0 control 61 adc0gth 0xc4 0 adc0 greater-than compare high 62 adc0gtl 0xc3 0 adc0 greater-than compare low 62 adc0h 0xbe 0 adc0 high 60 adc0l 0xbd 0 adc0 low 60 adc0lth 0xc6 0 adc0 less-than compare word high 63 adc0ltl 0xc5 0 adc0 less-than compare word low 63 adc0mx 0xbb 0 amux0 multiplexer channel select 66 b 0xf0 all pages b register 106 ckcon 0x8e all pages clock control 263 clksel 0xbd f clock select 263 cpt0cn 0x9b 0 comparator0 control 76 cpt0md 0x9d 0 comparator0 mode selection 77 cpt0mx 0x9f 0 comparator0 mux selection 79 crc0auto 0x96 f crc0 automatic control register 217 crc0cn 0x91 f crc0 control 215 crc0cnt 0x97 f crc0 automatic flash sector count 217 crc0data 0xd9 f crc0 data output 216 crc0flip 0x95 f crc0 bit flip 218 crc0in 0x94 f crc data input 216 rev. 1.0 133 c8051f70x/71x cs0cn 0x9a 0 cs0 control 88 cs0dh 0xaa 0 cs0 data high 90 cs0dl 0xa9 0 cs0 data low 90 cs0cf 0x9e 0 cs0 configuration 89 cs0md1 0xad 0 cs0 mode 1 94 cs0md2 0xbe f cs0 mode 2 95 cs0mx 0x9c 0 cs0 mux 97 cs0pm 0x9f f cs0 pin monitor 93 cs0se 0x93 f auto scan end channel 91 cs0ss 0x92 f auto scan start channel 91 cs0thh 0x97 0 cs0 digital compare threshold high 92 cs0thl 0x96 0 cs0 digital compare threshold low 92 derivid 0xec f derivative identification 128 dph 0x83 all pages data pointer high 104 dpl 0x82 all pages data pointer low 104 eeaddr 0xb6 all pages eeprom byte address 156 eecntl 0xc5 f eeprom control 158 eedata 0xd1 all pages eeprom byte data 157 eekey 0xc6 f eeprom protect key 159 eie1 0xe6 all pages extended interrupt enable 1 142 eie2 0xe7 all pages extended interrupt enable 2 143 eip1 0xce f extended interrupt priority 1 144 eip2 0xcf f extended interrupt priority 2 145 emi0cf 0xc7 f emif configuration 114 emi0cn 0xaa f emif control 113 emi0tc 0xee f emif timing control 119 flkey 0xb7 all pages flash lock and key 154 hwid 0xc4 f hardware identification 128 ie 0xa8 all pages interrupt enable 140 ip 0xb8 all pages interrupt priority 141 it01cf 0xe4 f int0/int1 configuration 147 oscicl 0xbf f internal osc illator calibration 173 oscicn 0xa9 f internal oscillator control 174 oscxcn 0xb5 f external oscillator control 176 p0 0x80 all pages port 0 latch 195 p0drv 0xf9 f port 0 drive strength 197 p0mask 0xf4 0 port 0 mask 192 p0mat 0xf3 0 port 0 match 193 table 20.2. special function registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved register address page description page c8051f70x/71x 134 rev. 1.0 p0mdin 0xf1 f port 0 input mode configuration 195 p0mdout 0xa4 f port 0 output mode configuration 196 p0skip 0xd4 f port 0 skip 196 p1 0x90 all pages port 1 latch 197 p1drv 0xfa f port 1 drive strength 199 p1mask 0xe2 0 p0 mask 193 p1mat 0xe1 0 p1 match 194 p1mdin 0xf2 f port 1 input mode configuration 198 p1mdout 0xa5 f port 1 output mode configuration 198 p1skip 0xd5 f port 1 skip 199 p2 0xa0 all pages port 2 latch 200 p2drv 0xfb f port 2 drive strength 202 p2mdin 0xf3 f port 2 input mode configuration 200 p2mdout 0xa6 f port 2 output mode configuration 201 p2skip 0xd6 f port 2 skip 201 p3 0xb0 all pages port 3 latch 202 p3drv 0xfc f port 3 drive strength 204 p3mdin 0xf4 f port 3 input mode configuration 203 p3mdout 0xaf f port 3 output mode configuration 203 p4 0xac all pages port 4 latch 204 p4drv 0xfd f port 4 drive strength 206 p4mdin 0xf5 f port 4 input mode configuration 205 p4mdout 0x9a f port 4 output mode configuration 205 p5 0xb3 all pages port 5 latch 206 p5drv 0xfe f port 5 drive strength 208 p5mdin 0xf6 f port 5 input mode configuration 207 p5mdout 0x9b f port 5 output mode configuration 207 p6 0xb2 all pages port 6 latch 208 p6drv 0xc1 f port 6 drive strength 210 p6mdin 0xf7 f port 6 input mode configuration 209 p6mdout 0x9c f port 6 output mode configuration 209 pca0cn 0xd8 all pages pca control 295 pca0cph0 0xfc 0 pca capture 0 high 300 pca0cph1 0xea 0 pca capture 1 high 300 pca0cph2 0xec 0 pca capture 2 high 300 pca0cpl0 0xfb 0 pca capture 0 low 300 pca0cpl1 0xe9 0 pca capture 1 low 300 pca0cpl2 0xeb 0 pca capture 2 low 300 table 20.2. special function registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved register address page description page rev. 1.0 135 c8051f70x/71x pca0cpm0 0xda f pca module 0 mode register 298 pca0cpm1 0xdb f pca module 1 mode register 298 pca0cpm2 0xdc f pca module 2 mode register 298 pca0h 0xfa 0 pca counter high 299 pca0l 0xf9 0 pca counter low 299 pca0md 0xed f pca mode 296 pca0pwm 0xa1 f pca pwm configuration 297 pcon 0x87 all pages power control 162 psctl 0x8f all pages program store r/w control 153 psw 0xd0 all pages program status word 107 ref0cn 0xd2 f voltage reference control 71 reg0cn 0xb9 f voltage regulator control 73 revid 0xad f revision id 129 rstsrc 0xef all pages reset source configuration/status 168 sbuf0 0x99 all pages uart0 data buffer 260 scon0 0x98 all pages uart0 control 259 sfrpage 0xa7 all pages sfr page 132 smb0adm 0xbb f smbus slave address mask 230 smb0adr 0xba f smbus slave address 229 smb0cf 0xc1 0 smbus configuration 225 smb0cn 0xc0 all pages smbus control 227 smb0dat 0xc2 0 smbus data 231 sp 0x81 all pages stack pointer 105 spi0cfg 0xa1 0 spi0 configuration 248 spi0ckr 0xa2 f spi0 clock rate control 250 spi0cn 0xf8 all pages spi0 control 249 spi0dat 0xa3 0 spi0 data 250 tcon 0x88 all pages timer/counter control 268 th0 0x8c all pages timer/counter 0 high 271 th1 0x8d all pages timer/counter 1 high 271 tl0 0x8a all pages timer/counter 0 low 270 tl1 0x8b all pages timer/counter 1 low 270 tmod 0x89 all pages timer/counter mode 269 tmr2cn 0xc8 all pages timer/counter 2 control 275 tmr2h 0xcd 0 timer/counter 2 high 277 tmr2l 0xcc 0 timer/counter 2 low 277 tmr2rlh 0xcb 0 timer/counter 2 reload high 276 tmr2rll 0xca 0 timer/counter 2 reload low 276 table 20.2. special function registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved register address page description page c8051f70x/71x 136 rev. 1.0 tmr3cn 0x91 0 timer/counter 3 control 281 tmr3h 0x95 0 timer/counter 3 high 283 tmr3l 0x94 0 timer/counter 3 low 283 tmr3rlh 0x93 0 timer/counter 3 reload high 282 tmr3rll 0x92 0 timer/counter 3 reload low 282 vdm0cn 0xff all pages vdd monitor control 166 wdtcn 0xe3 all pages watchdog timer control 170 xbr0 0xe1 f port i/o crossbar control 0 190 xbr1 0xe2 f port i/o crossbar control 1 191 all other sfr locations reserved table 20.2. special function registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved register address page description page rev. 1.0 137 c8051f70x/71x 21. interrupts the c8051f70x/71x includes an extended interrupt sys tem supporting several inte rrupt sources with two priority levels. the allocation of interrupt sources between on-chip peri pherals and external input pins var- ies according to the specific version of the device. ea ch interrupt source has one or more associated inter- rupt-pending flag(s) located in an sfr. when a peri pheral or external source meets a valid interrupt condition, the associated interrupt-pending flag is set to logic 1. if interrupts are enabled for the source, an interrupt re quest is generated when the interrupt-pending flag is set. as soon as execution of the current instructio n is complete, the cpu generates an lcall to a prede- termined address to begin execution of an interrupt service routine (isr). each isr must end with an reti instruction, which returns program execution to the next instruction that would have been executed if the interrupt request had not occurred. if interrupts are not enabled, the interrupt-pending flag is ignored by the hardware and program execution continues as normal. (t he interrupt-pending flag is set to logic 1 regard- less of the interrupt's enable/disable state.) each interrupt source can be individually enabled or disabled through the use of an associated interrupt enable bit in an sfr (ie?eie1). ho wever, interrupts must first be globally enabled by setting the ea bit (ie.7) to logic 1 before the individual interrupt enabl es are recognized. setting the ea bit to logic 0 disables all interrupt sources regardless of the individual interrupt-enable settings. some interrupt-pending flags are automatically cleare d by the hardware when the cpu vectors to the isr. however, most are not cleared by the hardware and must be cleared by software before returning from the isr. if an interrupt-pending flag remains set after the cpu completes the return-from-interrupt (reti) instruction, a new interr upt request will be gen erated immediately and the cpu will re-enter the isr after the completion of the next instruction. c8051f70x/71x 138 rev. 1.0 21.1. mcu interrupt sources and vectors the c8051f70x/71x mcus support 16 interrupt sources. software can simulate an interrupt by setting an interrupt-pending flag to logic 1. if interrupts are enabled fo r the flag, an in terrupt request w ill be generated and the cpu will vector to the isr address associated wit h the interrupt- pending flag. mcu interrupt sources, associated vector addresses, priority order and control bits are summarized in table 21.1. refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and t he behavior of its interrupt-pending flag(s). 21.1.1. interr upt priorities each interrupt source can be individually programmed to one of two priority levels: low or high. a low prior- ity interrupt service routine can be pr eempted by a high priority interrupt. a high priority interrupt cannot be preempted. each interrupt has an associated interrupt priority bit in an sfr (ip or eip1) used to configure its priority level. low priority is th e default. if two interrupts are recognized simultaneously, the interrupt with the higher priority is serviced first. if both interrupts have the same priority level, a fixed priority order is used to arbitrate, given in table 21.1. 21.1.2. interr upt latency interrupt response time depends on the state of the cpu when the interrupt occurs. pending interrupts are sampled and priority decoded each sys tem clock cycle. therefore, the fastest possible response time is 5 system clock cycles: 1 clock cycle to detect the interrup t and 4 clock cycles to complete the lcall to the isr. if an interrupt is pending when a reti is execut ed, a single instruction is executed before an lcall is made to service the pending interrupt. therefore, the maximum response time for an interrupt (when no other interrupt is currently being serviced or the new interrupt is of greater priority) occurs when the cpu is performing an reti instruct ion followed by a div as the next instructio n. in this case, th e response time is 18 system clock cycles: 1 clock cycle to detect the in terrupt, 5 clock cycles to execute the reti, 8 clock cycles to complete the div instruction and 4 clock cycl es to execute the lcall to the isr. if the cpu is executing an isr for an interr upt with equal or higher pr iority, the new interrupt will not be serviced until the current isr completes, including the reti and following instruction. rev. 1.0 139 c8051f70x/71x table 21.1. interrupt summary interrupt source interrupt vector priority order pending flag bit addressable? cleared by hw? enable flag priority control reset 0x0000 top none n/a n/a always enabled always highest external interrupt 0 (int0 ) 0x0003 0 ie0 (tcon.1) y y ex0 (ie.0) px0 (ip.0) timer 0 overflow 0x000b 1 tf0 (tcon.5) y y et0 (ie.1) pt0 (ip.1) external interrupt 1 (int1 ) 0x0013 2 ie1 (tcon.3) y y ex1 (ie.2) px1 (ip.2) timer 1 overflow 0x001b 3 tf1 (tcon.7) y y et1 (ie.3) pt1 (ip.3) uart0 0x0023 4 ri0 (scon0.0) ti0 (scon0.1) y n es0 (ie.4) ps0 (ip.4) timer 2 overflow 0x002b 5 tf2h (tmr2cn.7) tf2l (tmr2cn.6) y n et2 (ie.5) pt2 (ip.5) spi0 0x0033 6 spif (spi0cn.7) wcol (spi0cn.6) modf (spi0cn.5) rxovrn (spi0cn.4) y espi0 (ie.6) pspi0 (ip.6) smb0 0x003b 7 si (smb0cn.0) y n esmb0 (eie1.0) psmb0 (eip1.0) port match 0x0043 8 none n/a n/a emat (eie1.1) pmat (eip1.1) adc0 window compare 0x004b 9 ad0wint (adc0cn.3) y n ewadc0 (eie1.2) pwadc0 (eip1.2) adc0 conversion complete 0x0053 10 ad0int (adc0cn.5) y n eadc0 (eie1.3) padc0 (eip1.3) programmable counter array 0x005b 11 cf (pca0cn.7) ccfn (pca0cn.n) y n epca0 (eie1.4) ppca0 (eip1.4) comparator0 0x0063 12 cp0fif (cpt0cn.4) cp0rif (cpt0cn.5) nnecp0 (eie1.5) pcp0 (eip1.5) reserved timer 3 overflow 0x0073 14 tf3h (tmr3cn.7) tf3l (tmr3cn.6) nnet3 (eie1.7) pt3 (eip1.7) cs0 conversion complete 0x007b 15 cs0int (cs0cn.5) n n ecscpt (eie2.0) psccpt (eip2.0) cs0 greater than compare 0x0083 16 cs0cmpf (cs0cn.0) n n ecsgrt (eie2.1) pscgrt (eip2.1) c8051f70x/71x 140 rev. 1.0 21.2. interrupt re gister descriptions the sfrs used to enable the interrupt sources and set their priority level are described in this section. refer to the data sheet section associated with a pa rticular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). sfr address = 0xa8; sfr page = all pages; bi t-addressable sfr definition 21.1. ie: interrupt enable bit76543210 name ea espi0 et2 es0 et1 ex1 et0 ex0 type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7ea enable all interrupts. globally enables/disables all interrupts. it ov errides individual interrupt mask settings. 0: disable all interrupt sources. 1: enable each interrupt according to its individual mask setting. 6 espi0 enable serial peripheral interface (spi0) interrupt. this bit sets the masking of the spi0 interrupts. 0: disable all spi0 interrupts. 1: enable interrupt requests generated by spi0. 5et2 enable timer 2 interrupt. this bit sets the masking of the timer 2 interrupt. 0: disable timer 2 interrupt. 1: enable interrupt requests generated by the tf2l or tf2h flags. 4 es0 enable uart0 interrupt. this bit sets the masking of the uart0 interrupt. 0: disable uart0 interrupt. 1: enable uart0 interrupt. 3et1 enable timer 1 interrupt. this bit sets the masking of the timer 1 interrupt. 0: disable all timer 1 interrupt. 1: enable interrupt requests generated by the tf1 flag. 2 ex1 enable external interrupt 1. this bit sets the masking of external interrupt 1. 0: disable external interrupt 1. 1: enable interrupt requests generated by the int1 input. 1et0 enable timer 0 interrupt. this bit sets the masking of the timer 0 interrupt. 0: disable all timer 0 interrupt. 1: enable interrupt requests generated by the tf0 flag. 0 ex0 enable external interrupt 0. this bit sets the masking of external interrupt 0. 0: disable external interrupt 0. 1: enable interrupt requests generated by the int0 input. rev. 1.0 141 c8051f70x/71x sfr address = 0xb8; sfr page = all pages; bi t-addressable sfr definition 21.2. ip: interrupt priority bit76543210 name pspi0 pt2 ps0 pt1 px1 pt0 px0 type r r/w r/w r/w r/w r/w r/w r/w reset 10000000 bit name function 7 unused read = 1b, write = don't care. 6 pspi0 serial peripheral interface (spi 0) interrupt priority control. this bit sets the priority of the spi0 interrupt. 0: spi0 interrupt set to low priority level. 1: spi0 interrupt set to high priority level. 5pt2 timer 2 interrupt priority control. this bit sets the priority of the timer 2 interrupt. 0: timer 2 interrupt set to low priority level. 1: timer 2 interrupt set to high priority level. 4 ps0 uart0 interrupt priority control. this bit sets the priority of the uart0 interrupt. 0: uart0 interrupt set to low priority level. 1: uart0 interrupt set to high priority level. 3pt1 timer 1 interrupt priority control. this bit sets the priority of the timer 1 interrupt. 0: timer 1 interrupt set to low priority level. 1: timer 1 interrupt set to high priority level. 2 px1 external interrupt 1 priority control. this bit sets the priority of the external interrupt 1 interrupt. 0: external interrupt 1 se t to low priority level. 1: external interrupt 1 se t to high priority level. 1pt0 timer 0 interrupt priority control. this bit sets the priority of the timer 0 interrupt. 0: timer 0 interrupt set to low priority level. 1: timer 0 interrupt set to high priority level. 0 px0 external interrupt 0 priority control. this bit sets the priority of the external interrupt 0 interrupt. 0: external interrupt 0 se t to low priority level. 1: external interrupt 0 se t to high priority level. c8051f70x/71x 142 rev. 1.0 sfr address = 0xe6; sfr page = all pages sfr definition 21.3. eie1: ex tended interrupt enable 1 bit76543210 name et3 reserved ecp0 epca0 eadc0 ewadc0 emat esmb0 type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7et3 enable timer 3 interrupt. this bit sets the masking of the timer 3 interrupt. 0: disable timer 3 interrupt. 1: enable interrupt requests generated by the tf3l or tf3h flags. 6 reserved must write 0. 5ecp0 enable comparator0 (cp0) interrupt. this bit sets the masking of the cp0 rising edge or falling edge interrupt. 0: disable cp0 interrupts. 1: enable interrupt requests generated by the cp0rif and cp0fif flags. 4 epca0 enable programmable counte r array (pca0) interrupt. this bit sets the masking of the pca0 interrupts. 0: disable all pc a0 interrupts. 1: enable interrupt requests generated by pca0. 3 eadc0 enable adc0 conversion complete interrupt. this bit sets the masking of the adc0 conversion complete interrupt. 0: disable adc0 conversi on complete interrupt. 1: enable interrupt requests generated by the ad0int flag. 2ewadc0 enable window comparison adc0 interrupt. this bit sets the masking of adc0 window comparison interrupt. 0: disable adc0 window comparison interrupt. 1: enable interrupt requests generated by adc0 window compare flag (ad0wint). 1emat enable port match interrupts. this bit sets the masking of the port match event interrupt. 0: disable all port match interrupts. 1: enable interrupt requests generated by a port match. 0 esmb0 enable smbus (smb0) interrupt. this bit sets the masking of the smb0 interrupt. 0: disable all smb0 interrupts. 1: enable interrupt requests generated by smb0. rev. 1.0 143 c8051f70x/71x sfr address = 0xe7; sfr page = all pages sfr definition 21.4. eie2: ex tended interrupt enable 2 bit76543210 name ecsgrt ecscpt type rrrrrrr/wr/w reset 00000000 bit name function 7:2 unused read = 000000b; write = don?t care. 1ecsgrt enable capacitive sense greater than comparator interrupt. 0: disable capacitive sense greater than comparator interrupt. 1: enable interrupt requests generated by cs0cmpf. 0ecscpt enable capacitive sense conversion complete interrupt. 0: disable capacitive sense co nversion comple te interrupt. 1: enable interrupt requests generated by cs0int. c8051f70x/71x 144 rev. 1.0 sfr address = 0xce; sfr page = f sfr definition 21.5. eip1: extended interrupt priority 1 bit76543210 name pt3 reserved pcp0 ppca0 padc0 pwadc0 pmat psmb0 type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7pt3 timer 3 interrupt priority control. this bit sets the priority of the timer 3 interrupt. 0: timer 3 interrupt set to low priority level. 1: timer 3 interrupt set to high priority level. 6 reserved must write 0b. 5pcp0 comparator0 (cp0) interru pt priority control. this bit sets the priority of the cp 0 rising edge or falling edge interrupt. 0: cp0 interrupt set to low priority level. 1: cp0 interrupt set to high priority level. 4 ppca0 programmable counter array (pca0) interrupt priority control. this bit sets the priority of the pca0 interrupt. 0: pca0 interrupt set to low priority level. 1: pca0 interrupt set to high priority level. 3 padc0 adc0 conversion complete interrupt priority control. this bit sets the priority of the adc0 conversion complete interrupt. 0: adc0 conversion complete inte rrupt set to low priority level. 1: adc0 conversion complete interrupt set to high priority level. 2pwadc0 adc0 window comparator interrupt priority control. this bit sets the priority of the adc0 window interrupt. 0: adc0 window interrupt se t to low priority level. 1: adc0 window interrupt set to high priority level. 1pmat port match interrupt priority control. this bit sets the priority of the port match event interrupt. 0: port match interrupt se t to low priority level. 1: port match interrupt se t to high priority level. 0 psmb0 smbus (smb0) interrupt priority control. this bit sets the priority of the smb0 interrupt. 0: smb0 interrupt set to low priority level. 1: smb0 interrupt set to high priority level. rev. 1.0 145 c8051f70x/71x sfr address = 0xcf; sfr page = f sfr definition 21.6. eip2: extended interrupt priority 2 bit76543210 name reserved reserved reserved reserv ed reserved reserved pscgrt psccpt type rrrrrrr/wr/w reset 00000000 bit name function 7:2 reserved must write 000000b. 1 pscgrt capacitive sense greater than comparator priority control. this bit sets the priority of the capaciti ve sense greater than comparator interrupt. 0: cs0 greater than comparator inte rrupt set to low priority level. 1: cs0 greater than comparator set to high priority level. 0 psccpt capacitive sense conversion complete priority control. this bit sets the priority of the capacitive sense conversion complete interrupt. 0: cs0 conversion complete set to low priority level. 1: cs0 conversion complete set to high priority level. c8051f70x/71x 146 rev. 1.0 21.3. int0 and int1 external interrupts the int0 and int1 external interrupt sources are configurable as active high or low, edge or level sensi- tive. the in0pl (int0 polarity) and in1pl (int1 polarity) bits in the it01cf register select active high or active low; the it0 and it1 bits in tcon (section ?33.1. timer 0 and timer 1? on page 264) select level or edge sensitive. the table below lis ts the possible configurations. int0 and int1 are assigned to port pins as defined in the it01cf register (see sfr definition 21.7). note that int0 and int0 port pin assignments are independent of any crossbar assignments. int0 and int1 will monitor their assigned port pins wit hout disturbing the peripheral that was assigned the port pin via the crossbar. to assign a port pin only to int0 and/or int1 , configure the crossbar to skip the selected pin(s). this is accomplished by setting the associated bit in register xbr0 (see section ?28.3. priority crossbar decoder? on page 185 for complete details on configuring the crossbar). ie0 (tcon.1) and ie1 (tcon.3) serve as the interrupt-pending flags for the int0 and int1 external inter- rupts, respectively. if an int0 or int1 external interrupt is configured as edge-sensitive, the corresponding interrupt-pending flag is automatically cleared by the hardware when the cpu vectors to the isr. when configured as level sensitive, the interrupt-pending flag remains logic 1 while the input is active as defined by the corresponding polarity bit (in0pl or in1pl); th e flag remains logic 0 while the input is inactive. the external interrupt source must hold the input active until the interrupt request is recognized. it must then deactivate the interrupt request bef ore execution of the isr completes or another interr upt request will be generated. it0 in0pl int0 interrupt it1 in1pl int1 interrupt 1 0 active low, edge sensitive 1 0 active low, edge sensitive 1 1 active high, edge sensitive 1 1 active high, edge sensitive 0 0 active low, level sensitive 0 0 active low, level sensitive 0 1 active high, level sensitive 0 1 active high, level sensitive rev. 1.0 147 c8051f70x/71x sfr address = 0xe4; sfr page = f sfr definition 21.7. it01cf: int0 /int1 configuration bit76543210 name in1pl in1sl[2:0] in0pl in0sl[2:0] type r/w r/w r/w r/w reset 00000001 bit name function 7in1pl int1 polarity. 0: int1 input is active low. 1: int1 input is active high. 6:4 in1sl[2:0] int1 port pin se lection bits. these bits select which port pin is assigned to int1 . note that this pin assignment is independent of the crossbar; int1 will monitor the assigned port pin without disturb- ing the peripheral that has been assigned t he port pin via the crossbar. the crossbar will not assign the port pin to a peripheral if it is configured to skip the selected pin. 000: select p0.0 001: select p0.1 010: select p0.2 011: select p0.3 100: select p0.4 101: select p0.5 110: select p0.6 111: select p0.7 3in0pl int0 polarity. 0: int0 input is active low. 1: int0 input is active high. 2:0 in0sl[2:0] int0 port pin se lection bits. these bits select which port pin is assigned to int0 . note that this pin assignment is independent of the crossbar; int0 will monitor the assigned port pin without disturb- ing the peripheral that has been assigned t he port pin via the crossbar. the crossbar will not assign the port pin to a peripheral if it is configured to skip the selected pin. 000: select p0.0 001: select p0.1 010: select p0.2 011: select p0.3 100: select p0.4 101: select p0.5 110: select p0.6 111: select p0.7 c8051f70x/71x 148 rev. 1.0 22. flash memory on-chip, re-programmable flash memory is included fo r program code and non-volatile data storage. the flash memory can be programmed in-system through the c2 interface or by software using the movx write instruction. once cleared to logic 0, a flash bit mu st be erased to set it back to logic 1. flash bytes would typically be erased (set to 0xff) before being reprogrammed. the write and erase operations are automatically timed by hard ware for proper execution; data polling to determine the end of th e write/erase operations is not required. code execution is st alled during flash write/erase operations. refer to table 9.6 for complete flash memory electrical characteristics. 22.1. programming the flash memory the simplest means of programming the flash memo ry is through the c2 interface using programming tools provided by silicon laboratories or a th ird party vendor. this is the only means for programming a non-initialized device. for details on the c2 commands to program flash memory, see section ?35. c2 interface? on page 301. the flash memory can be programmed by software using the movx write instru ction with the address and data byte to be programmed provided as normal operands. before programming flash memory using movx, flash programming operations must be enabled by: (1) setting the pswe program store write enable bit (psctl.0) to logic 1 (this directs the movx writes to target flash memory); and (2) writing the flash key codes in sequence to the flash lock register (flkey). the pswe bit remains set un til cleared by software. note: a minimum sysclk frequency is required for writing or erasing flash memory, as detailed in section ?table 9.6. flash electrical characteristics? on page 50. for detailed guidelines on programming flash from fi rmware, please see section ?22.4. flash write and erase guidelines? on page 150. to ensure the integrity of the flash contents, the on -chip vdd monitor must be enabled and enabled as a reset source in any system that includes code that writes and/or erases flash memory from software. fur- thermore, there should be no delay between enabling the v dd monitor and enabling the v dd monitor as a reset source. any attempt to write or erase flash memory while the v dd monitor is disabled, or not enabled as a reset source, will ca use a flash error device reset. 22.1.1. flash lock and key functions flash writes and erases by user so ftware are protected with a lock and key function. th e flash lock and key register (flkey) must be writ ten with the correct key codes, in sequence, be fore flash operations may be performed. the key codes are: 0xa5, 0xf1. the timing does not matter, but the codes must be written in order. if the key codes are written out of or der, or the wrong codes are written, flash writes and erases will be disabled until the next system reset. flash writes and eras es will also be disabled if a flash write or erase is attempted before the key codes have been written properly. the flash lock resets after each write or erase; the key codes must be writte n again before a following flash operation can be per- formed. the flkey register is det ailed in sfr definition 22.2. 22.1.2. flash erase procedure the flash memory is organized in 512-byte pages. the erase operation applies to an entire page (setting all bytes in the page to 0xff). to erase an en tire 512-byte page, perform the following steps: 1. save current interrupt state and disable interrupts. 2. set the psee bit (register psctl). 3. set the pswe bit (register psctl). 4. write the first key code to flkey: 0xa5. 5. write the second key code to flkey: 0xf1. rev. 1.0 149 c8051f70x/71x 6. using the movx instruction, write a data byte to any location within the 512-byte page to be erased. 7. clear the pswe and psee bits. 8. restore previous interrupt state. steps 4?6 must be repeated for each 512-byte page to be erased. note: flash security settings may prevent erasure of some flash pages, such as the reserved area and the page containing the lock bytes. for a summary of flash security settings and restrictions affecting flash erase operations, please see section ?22.3. security options? on page 149. 22.1.3. flash write procedure a write to flash memory can clear bits to logic 0 but cannot set them; only an erase operation can set bits to logic 1 in flash. a byte location to be programmed should be erased before a new value is written. the recommended procedure for writing a si ngle byte in flash is as follows: 1. save current interrupt state and disable interrupts. 2. ensure that the flash byte has been erased (has a value of 0xff). 3. set the pswe bit (register psctl). 4. clear the psee bit (register psctl). 5. write the first key code to flkey: 0xa5. 6. write the second key code to flkey: 0xf1. 7. using the movx instruction, write a single data byte to the desired location within the 512-byte sector. 8. clear the pswe bit. 9. restore previous interrupt state. steps 5?7 must be repeated for each byte to be written. note: flash security settings may prevent writes to some ar eas of flash, such as the reserved area. for a summary of flash security settings and restrictions affecting fl ash write operations, please see section ?22.3. security options? on page 149. 22.2. non-volati le data storage the flash memory can be used for non-volatile data storage as well as program code. this allows data such as calibration coefficients to be calculated and stored at run time. data is written using the movx write instruction and read us ing the movc instruction. note: movx read instructions always target xram. 22.3. security options the cip-51 provides security options to protect the flash memory from inadvertent modification by soft- ware as well as to prevent the viewing of proprietary program code and constants. the program store write enable (bit pswe in register psctl) and th e program store erase enable (bit psee in register psctl) bits protect the flash memory from accidental modification by software. pswe must be explicitly set to 1 before software can modify the flash memory; both pswe and psee must be set to 1 before soft- ware can erase flash memory. additional security features prevent proprietary program code and data constants from being read or altered across the c2 interface. a security lock byte located at the last byte of fl ash user space offers protection of the flash program memory from access (reads, writes, and erases) by u nprotected code or the c2 in terface. the flash secu- rity mechanism allows the user to lock all flash page s, starting at page 0, by writing a non-0xff value to the lock byte. note that writing a non-0xff value to the lock byte will lock all pages of flash from reads, writes, and erases, including the page containing the lock byte. the level of flash security depends on the flash access method. the three flash access methods that can be restricted are reads, writes, an d erases from the c2 debug interface, user firmware executing on c8051f70x/71x 150 rev. 1.0 unlocked pages, and user firmware executing on locked pages. table 22.1 summarizes the flash security features of the c8051f70x/71x devices. 22.4. flash write and erase guidelines any system which contains routines which write or er ase flash memory from software involves some risk that the write or erase ro utines will execute unin tentionally if the cpu is op erating outside its specified operating range of vdd, system clock frequency, or te mperature. this accidental execution of flash modi- fying code can result in alteration of flash memory contents causing a system failure that is only recover- able by re-flashing the code in the device. to help prevent the accidental modi fication of flash by firmware, the vdd monitor must be enabled and enabled as a reset source on c8051f70x/71x devi ces for the flash to be successfully modified. if either the vdd monitor or the vdd monitor reset source is not enabled, a flash error device reset will be generated when the firmware attempts to modify the flash. table 22.1. flash security summary action c2 debug interface user firmware executing from: an unlocked page a locked page read, write or erase unlocked pages (except page with lock byte) permitted permitted permitted read, write or erase locked pages (except page with lock byte) not permitted fedr permitted read or write page containing lock byte (if no pages are locked) permitted permitted permitted read or write page containing lock byte (if any page is locked) not permitted fedr permitted read contents of lock byte (if no pages are locked) permitted permitted permitted read contents of lock byte (if any page is locked) not permitted fedr permitted erase page containing lock byte (if no pages are locked) permitted fedr fedr erase page containing lock byte - unlock all pages (if any page is locked) only by c2de fedr fedr lock additional pages (change '1's to '0's in the lock byte) not permitted fedr fedr unlock individual pages (change '0's to '1's in the lock byte) not permitted fedr fedr read, write or erase reserved area not permitted fedr fedr c2de - c2 device erase (erases all flash pages including the page containing the lock byte) fedr - not permitted; causes flash error device reset (ferror bit in rstsrc is '1' after reset) - all prohibited operations that are performed via the c2 interface are ignored (do not cause device reset). - locking any flash page also locks th e page containing the lock byte. - once written to, the lock byte cannot be modifi ed except by performing a c2 device erase. - if user code writes to the lock byte, the lock does not take effect until the next device reset. rev. 1.0 151 c8051f70x/71x the following guidelines are recomme nded for any system that contains routines which write or erase flash from code. 22.4.1. vdd maintenance and the vdd monitor 1. if the system power supply is subject to voltage or current "spikes," add sufficient transient protection devices to the power supply to ensure that the supply voltages listed in the absolute maximum ratings table are not exceeded. 2. make certain that the minimum vdd rise time specification of 1 ms is met. if the system cannot meet this rise time specification, then add an external vdd brownout circuit to the /r st pin of the device that holds the device in reset until vdd reaches the mini mum device operating voltage and re-asserts /rst if vdd drops below the minimum device operating voltage. 3. keep the on-chip vdd monitor enabled and enable the vdd monitor as a reset source as early in code as possible. this should be the fi rst set of instructions executed after the reset vector. for c-based systems, this will involve modifyin g the startup code a dded by the c compiler. see your compiler documentation for more details. make certain that th ere are no delays in software between enabling the vdd monitor and enabling the vdd monitor as a reset source. code examples showing this can be found in ?an201: writing to flash from firmware," available from th e silicon laboratories web site. note: on c8051f70x/71x devices, both the vdd monitor and the vdd monitor reset source must be enabled to write or erase flash without generating a flash error device reset. on c8051f70x/71x devices, both the vdd monitor and the vdd monitor reset source are enabled by hardware after a power-on reset. 4. as an added precaution, explicitly enable the vdd monitor and enable the vdd monitor as a reset source inside the functions that write and erase flash memory. the vdd monitor enable instructions should be placed just after the in struction to set pswe to a 1, but before the flash write or erase operation instruction. 5. make certain that all writes to the rstsrc (reset sources) register use di rect assignment operators and explicitly do not use the bit-wise operators (such as and or or). for example, "rstsrc = 0x02" is correct, but "rstsrc |= 0x02" is incorrect. 6. make certain that all writes to the rstsrc register explicitly set the porsf bi t to a 1. areas to check are initialization code which enables other reset sources, such as the missing clock detector or comparator, for example, and instructions which force a software reset. a global search on "rstsrc" can quickly verify this. 22.4.2. pswe maintenance 7. reduce the number of places in code where the pswe bit (b0 in psctl) is set to a 1. there should be exactly one routine in code that sets pswe to a 1 to write flash bytes and one routine in code that sets both pswe and psee both to a 1 to erase flash pages. 8. minimize the number of variable accesses while pswe is set to a 1. handle pointer address updates and loop maintenance outside the "pswe = 1;... pswe = 0;" area. code examples showing this can be found in ?an201: writing to flash from firmware," available from th e silicon laboratories web site. 9. disable interrupts prior to setting pswe to a 1 and leave them disabled until after pswe has been reset to 0. any interrupts posted during the flash write or erase operation will be serviced in priority order after the flash operation has been completed a nd interrupts have been re-enabled by software. 10.make certain that the flash write and erase poin ter variables are not located in xram. see your compiler documentation for instructions regarding how to explicitly locate variab les in different memory areas. 11. add address bounds checking to th e routines that write or erase flas h memory to ensure that a routine called with an illegal address does not result in modification of the flash. c8051f70x/71x 152 rev. 1.0 22.4.3. system clock 12.if operating from an external crystal, be advised th at crystal performance is susceptible to electrical interference and is sensitive to layout and to changes in temperature. if the system is operating in an electrically noisy environment, use the internal oscillator or use an external cmos clock. 13.if operating from the external oscillator, switch to the internal oscillator du ring flash write or erase operations. the external oscillator can continue to run, and the cpu can switch back to the external oscillator after the flash operation has completed. additional flash recommendations and example code ca n be found in ?an201: writing to flash from firm- ware, " available from the silic on laboratories web site. rev. 1.0 153 c8051f70x/71x sfr address =0x8f; sfr page = all pages sfr definition 22.1. psctl: program store r/w control bit76543210 name psee pswe type rrrrrrr/wr/w reset 00000000 bit name function 7:2 unused read = 000000b, write = don?t care. 1 psee program store erase enable. setting this bit (in combination with pswe) allows an entire page of flash program memory to be erased. if this bit is logic 1 and flash writes are enabled (pswe is logic 1), a write to flash memory using the movx instruction will erase the entire page that contains the location addressed by the movx instruction. the value of the data byte written does not matter. 0: flash program memory erasure disabled. 1: flash program memory erasure enabled. 0 pswe program store write enable. setting this bit allows writing a byte of data to the flash program memory using the movx write instruction. the flash location should be erased before writing data. 0: writes to flash program memory disabled. 1: writes to flash program memory enabl ed; the movx write instruction targets flash memory. c8051f70x/71x 154 rev. 1.0 sfr address = 0xb7; sfr page = all pages sfr definition 22.2. flk ey: flash lock and key bit76543210 name flkey[7:0] type r/w reset 00000000 bit name function 7:0 flkey[7:0] flash lock and key register. write: this register provides a lock and key func tion for flash erasures and writes. flash writes and erases are enabled by writing 0xa5 follo wed by 0xf1 to the flkey regis- ter. flash writes and erases are automatically disabled after the next write or erase is complete. if any writes to flkey are performed incorrectly, or if a flash write or erase operation is attempted while these operations are disa bled, the flash will be perma- nently locked from writes or erasures until the next device reset. if an application never writes to flash, it can intentionally lock the flash by writing a non-0xa5 value to flkey from software. read: when read, bits 1?0 indicate the current flash lock state. 00: flash is write/erase locked. 01: the first key code has been written (0xa5). 10: flash is unlocked (writes/erases allowed). 11: flash writes/erases disabled until the next reset. rev. 1.0 155 c8051f70x/71x 23. eeprom c8051f700/1/4/5/8/9 and c8051f712/3 devices have har dware which emulates 32 bytes of non-volatile, byte-programmable eeprom data space. the module mirrors each non-volatile byte through 32 bytes of volatile data space. this data sp ace can be access ed indirectly through eead dr and eedata. users can copy the complete 32-byte image bet ween eeprom space and volatile space usin g controls in the eecntl sfr. figure 23.1. eeprom block diagram 23.1. ram reads and writes in order to perform eeprom read s and writes, the eeprom control lo gic must be enabled by setting eeen (eecntl.7). 32 bytes of ram can be accessed indirectly through eeaddr and eedata. to write to a byte of ram, write address of byte to eeaddr and then write the va lue to be writte n to eedata. to read a byte from ram, write address of byte to be read to eeaddr. the value stored at that address can then be read from eedata. 23.2. auto increment when autoinc (eecntl.0) is set, eeaddr will increment by one afte r each write to eedata and each read from eedata. when auto increment is enabled and eeaddr reaches the top address of dedicated ram space, the next write to or read from eedata will cause eeaddr to wrap along the address bound- ary, which will set the address to 0. 23.3. interfacing with the eeprom the eeprom is accessed through the dedicated 32 bytes of ram. wr ites to eeprom are allowed only after writes have b een enabled (see ?23.4. eeprom security? ). t he contents of the eeprom can be uploaded to the ram by setting eeread (eecntl.2). contents of ram can be downloaded to eeprom by setting eewrt (eentl.1). note: a minimum sysclk frequency is required for writ ing eeprom memory, as detailed in section ? table 9.9. eeprom electrical characteristics ? on page 52 . eekey 32 bytes eeprom 32 bytes ram eeprom control logic eeaddr eedata eecntl eeen eeread eewrt autoinc c8051f70x/71x 156 rev. 1.0 23.4. eeprom security ram can only be downloaded to eep rom after firmware writes a seq uence of two bytes to eekey. in order to enable eeprom writes: 1. write the first eeprom key code byte to eekey: 0x55 2. write the second eeprom ke y code byte to eekey: 0xaa after a eeprom writes have been enabled and a single write has executed, the control logic locks eeprom writes until the two- byte unlock sequence has be en entered into eekey again. the protection state of the eepr om can be observed by reading eepstate (eekey2:0). this state can be read at any time without affect ing the eeprom?s protection state. if the two-byte unlock sequence is entered incorrectly, or if a write is attempted without first entering the two-byte sequence, eeprom writes will be locked until the next power-on reset. sfr address = 0xb6; sfr page = all pages sfr definition 23.1. eea ddr: eeprom byte address bit76543210 name eeaddr[4:0] type rrr r/w reset 00000000 bit name description 7:5 unused read = 000b; write = don?t care 4:0 eeaddr[4:0] eeprom byte address selects one of 32 eeprom bytes to read/write. rev. 1.0 157 c8051f70x/71x sfr address = 0xd1; sfr page = all pages sfr definition 23.2. eedata: eeprom byte data bit76543210 name eedata[7:0] type r/w reset 11111111 bit name description write read 7:0 eedata[7:0] e2prom data the eedata register is used to read bytes from the eeprom space and write bytes to eeprom space. writes byte to location stored in eeaddr. returns contents at loca- tion stored in eeaddr. c8051f70x/71x 158 rev. 1.0 sfr address = 0xc5; sfr page = f sfr definition 23.3. eec ntl: eeprom control bit76543210 name eeen eeread eewrt autoinc type r/w r r/w reset 00000001 bit name description 7 eeen eeprom enable. 0: eeprom control logic disabled. 1: eeprom control logic enabled. eeprom reads and writes can be performed. 6:4 reserved reserved. read = variable; write = don?t care 3 reserved reserved. read = 0b, write = 0 2 eeread eeprom 32-byte read. 0: does nothing. 1: 32 bytes of eeprom data will be read from flash to internal ram. 1eewrite eeprom 32-byte write. 0: does nothing. 1: 32 bytes of eeprom data will be written from internal ram to flash. 0 autoinc auto increment. 0: disable auto-increment. 1: enable auto-increment. rev. 1.0 159 c8051f70x/71x sfr address = 0xc6; sfr page = f sfr definition 23.4. eekey: eeprom protect key bit76543210 name eekey eepstate/eekey type wr/w reset 00000000 bit name description write read 7:0 eekey eeprom key. protects the eeprom from inadvertent writes and erases. the sequence 0x55 0xaa must be written to enable eeprom writes and erases 1:0 eepstate eeprom protection state. these bytes show whether flash writes/erases have been enabled, disabled, or locked. 00: write/erase is not enabled 01: the first key has been written 10: write/erase is enabled 11: eeprom is locked from further writes/erases c8051f70x/71x 160 rev. 1.0 24. power management modes the c8051f70x/71x devices have three software pr ogrammable power management modes: idle, stop, and suspend. idle mode and stop mode are part of the standard 8051 architecture, while suspend mode is an enhanced power-saving mode implemented by the hi gh-speed oscillator peripheral. idle mode halts the cpu while leaving the peripherals and clocks active. in stop mode, the cpu is halted, all interrupts and timers (except the missing clock de tector) are inactive, and the internal oscillator is stopped (analog peripherals remain in their se lected states; the external o scillator is not affected). sus- pend mode is similar to stop mode in that the internal oscillator an d cpu are halted, but the device can wake on events such as a port mismatch, comparator low output, or a timer 3 overflow. since clocks are running in idle mode, power consumption is dependent upon the system clock frequency and the number of peripherals left in active mode before entering idle. stop mode and suspend mode consume the least power because the majority of the device is shut down with no clocks active. sfr definition 24.1 describes the power control register (pcon) used to control the c8051f70x/71x's stop and idle power manage- ment modes. suspend mode is cont rolled by the suspend bit in the oscicn register (sfr definition 27.3). although the c8051f70x/71x has idle, stop, and susp end modes available, more control over the device power can be achieved by enabling/disabling individ ual peripherals as needed. each analog peripheral can be disabled when not in use and placed in low power mode. digital peripherals, such as timers or serial buses, draw little power when they are not in use. turning off oscillators lowers power consumption considerably, at the expense of reduced functionality. 24.1. idle mode setting the idle mode select bit (pcon.0) causes the hardware to halt the cpu and enter idle mode as soon as the instruction that sets the bit completes execution. all internal registers and memory maintain their original data. all analog and digital peripherals can remain active during idle mode. idle mode is terminated when an enabled interrupt is asserted or a reset occurs. the assertion of an enabled interrupt will cause the idle mode selection bit (pcon.0) to be cleared and the cpu to resume operation. the pen ding interrupt will be serviced and the next in struction to be executed after the return from interrupt (reti) will be the instruction imme diately following the one that set the idle mode select bit. if idle mode is terminated by an internal or external reset, the cip-51 performs a normal reset sequence and begins program execution at address 0x0000. note: if the instruction following the write of the idle bit is a single-byte instruction and an interrupt occurs during the execution phase of the instruction that sets the idle bit, the cpu may not wake from idle mode when a future interrupt occurs. therefore, instructions that set the idle bit should be followed by an instruction that has two or more opcode bytes, for example: // in ?c?: pcon |= 0x01; // set idle bit pcon = pcon; // ... followed by a 3-cycle dummy instruction ; in assembly: orl pcon, #01h ; set idle bit mov pcon, pcon ; ... followed by a 3-cycle dummy instruction if enabled, the watchdog timer (wdt) will eventually cause an internal watchdog reset a nd thereby termi- nate the idle mode. this feature protects the system from an unintended permanent shutdown in the event of an inadvertent write to the pcon register. if this behavior is not desired, the wdt may be disabled by software prior to entering the idle mo de if the wdt was initially configured to allow this operation. this pro- vides the opportunity for additional power savings, allo wing the system to remain in the idle mode indefi- nitely, waiting for an external stimulus to wake up the system. refer to section ?26. watchdog timer? on page 169 for more information on the use and configuration of the wdt. rev. 1.0 161 c8051f70x/71x 24.2. stop mode setting the stop mode select bit (pcon.1) causes the co ntroller core to enter stop mode as soon as the instruction that sets the bit complete s execution. in stop mode the intern al oscillator, cpu, and all digital peripherals are stopp ed; the state of the external oscillator circ uit is not affected. each analog peripheral (including the external oscillator circ uit) may be shut down individually prior to en tering stop mode. stop mode can only be terminated by an internal or external reset. on reset, the device performs the normal reset sequence and begins program execution at address 0x0000. if enabled, the missing clock detect or will cause an internal reset and ther eby terminate th e stop mode. the missing clock detector should be disabled if the cpu is to be put to in stop mode for longer than the mcd timeout of 100 s. 24.3. suspend mode suspend mode allows a system running from the internal oscillator to go to a very low power state similar to stop mode, but the processor can be awakened by certain events without requiring a reset of the device. setting the suspend bit (oscicn.5) causes the hardware to halt the cpu and the high-frequency inter- nal oscillator, and go into suspend m ode as soon as the inst ruction that sets the bit completes execution. all internal registers and memory main tain their original data. most digital peripherals are not active in sus- pend mode. the exception to this is the port match feature and timer 3, when it is run from an external oscillator source. note that the clock divider bits clkdiv[2:0] in register clksel must be set to "divide by 1" when entering suspend mode. suspend mode can be terminated by five types of events, a port match (described in section ?28.5. port match? on page 192), a timer 3 overflow (described in section ?33.3. timer 3? on page 278), a comparator low output (if enabled), a capacitive sense greater-than comparator interrupt, or a device reset event. in order to run timer 3 in suspend mode, the timer must be configured to clock from the external clock source/8. when suspend mode is termi nated, the device will continue execution on the instruction follow- ing the one that set the suspend bit. if the wake event (port match or timer 3 overflow) was configured to generate an interrupt, the interrupt will be servic ed upon waking the device. if suspend mode is terminated by an internal or external reset, the cip-51 performs a normal reset sequence and begins program execu- tion at address 0x0000. note: the device will still enter suspend mode if a wake source is "pending", and the device will not wake on such pending sources. it is important to ensure that the intended wake source will trigger after the device enters suspend mode. for example, if a cs0 conversion completes and the interrupt fires before the device is in suspend mode, that interrupt cannot trigger the wake event. because port match events are level-sensitive, pre-existing port match events will trigger a wake, as long as the matc h condition is still present when the device enters suspend. c8051f70x/71x 162 rev. 1.0 sfr address = 0x87; sfr page = all pages sfr definition 24.1. pcon: power control bit76543210 name gf[5:0] stop idle type r/w r/w r/w reset 00000000 bit name function 7:2 gf[5:0] general purpose flags 5?0. these are general purpose flags for use under software control. 1stop stop mode select. setting this bit will place the cip-51 in st op mode. this bit will always be read as 0. 1: cpu goes into stop mode (internal oscillator stopped). 0idle idle: idle mode select. setting this bit will place the cip-51 in idle mode. this bit will always be read as 0. 1: cpu goes into idle mode. (shuts off clo ck to cpu, but clock to timers, interrupts, serial ports, and analog peripherals are still active.) rev. 1.0 163 c8051f70x/71x 25. reset sources reset circuitry allows the controller to be easily placed in a predefined default condition. on entry to this reset state, th e following occur: ?? cip-51 halts program execution ?? special function registers (sfrs) are initialized to their defined reset values ?? external port pins are forced to a known state ?? interrupts and timers are disabled. all sfrs are reset to the predefined values noted in the sfr detailed descriptions. the contents of internal data memory are unaffected during a reset; any prev iously stored data is preserved. however, since the stack pointer sfr is reset, the stack is effectively lo st, even though the data on the stack is not altered. the port i/o latches are reset to 0xff (all logic ones) in open-drain mode. weak pullups are enabled dur- ing and after the reset. for v dd monitor and power-on resets, the rst pin is driven low until the device exits the reset state. on exit from the reset state, the program counter (pc) is reset, and the system clock defaults to the inter- nal oscillator. the watchdog timer is enabled with the system clock divided by 12 as its clock source. pro- gram execution begins at location 0x0000. figure 25.1. reset sources pca wdt missing clock detector (one- shot) (software reset) system reset reset funnel px.x px.x en swrsf system clock cip-51 microcontroller core extended interrupt handler en wdt enable mcd enable errant flash operation rst (wired-or) power on reset '0' + - comparator 0 c0rsef vdd + - supply monitor enable c8051f70x/71x 164 rev. 1.0 25.1. power-on reset during power-up, the device is held in a reset state and the rst pin is driven low until v dd settles above v rst . a delay occurs before the device is released from reset; the delay decreases as the v dd ramp time increases (v dd ramp time is defined as how fast v dd ramps from 0 v to v rst ). figure 25.2. plots the power-on and v dd monitor reset timing. the maximum v dd ramp time is 1 ms; slower ramp times may cause the device to be released from reset before v dd reaches the v rst level. for ramp times less than 1 ms, the power-on reset delay (t pordelay ) is typically less than 10 ms. on exit from a power-on reset, the porsf flag (rst src.1) is set by hardware to logic 1. when porsf is set, all of the other reset flags in the rstsrc regist er are indeterminate (porsf is cleared by all other resets). since all resets cause program execution to begin at the same location (0x0000) software can read the porsf flag to determine if a power-up was t he cause of reset. the content of internal data mem- ory should be assumed to be undefined after a power-on reset. the v dd monitor is enabled following a power-on reset. figure 25.2. power-on and v dd monitor reset timing power-on reset vdd monitor reset rst t v dd supply logic high logic low t pordelay v dd v rst v dd rev. 1.0 165 c8051f70x/71x 25.2. power-fail reset / v dd monitor when a power-down transition or power irregularity causes v dd to drop below v rst , the power supply monitor will drive the rst pin low and hold the cip-51 in a reset state (see figure 25.2). when v dd returns to a level above v rst , the cip-51 will be released fr om the reset state. even though internal data memory contents are not altered by the power-fail reset, it is impossible to determine if v dd dropped below the level required for data retention. if the porsf flag reads 1, the data may no longer be valid. the v dd monitor is enabled after power-on resets. its defined state (enabled /disabled) is not altered by any other reset source. for example, if the v dd monitor is disabled by code and a software reset is performed, the v dd monitor will still be disabled after the reset. important note: if the v dd monitor is being turned on from a disabled state, it should be enabled before it is selected as a reset source. selecting the v dd monitor as a reset source before it is enabled and stabi- lized may cause a system reset. in some applications, this reset may be undesirable. if this is not desirable in the application, a delay should be introduced betwe en enabling the monitor and selecting it as a reset source. the procedure for enabling the v dd monitor and configuring it as a reset source from a disabled state is shown below: 1. enable the v dd monitor (vdmen bit in vdm0cn = 1). 2. if necessary, wait for the v dd monitor to stabilize. 3. select the v dd monitor as a reset source (porsf bit in rstsrc = 1). see figure 25.2 for v dd monitor timing; note that the power-on -reset delay is not incurred after a v dd monitor reset. see section ?9. electri cal characteristics? on page 47 for complete electrical characteristics of the v dd monitor. c8051f70x/71x 166 rev. 1.0 sfr address = 0xff; sfr page = all pages 25.3. external reset the external rst pin provides a means for external circuitry to force the device into a reset state. assert- ing an active-low signal on the rst pin generates a reset; an external pullup and/or decoupling of the rst pin may be necessary to avoid erroneous noise-induce d resets. see section ?9. e lectrical characteristics? on page 47 for complete rst pin specifications. the pinrsf flag (rstsr c.0) is set on exit from an exter- nal reset. 25.4. missing cl ock detector reset the missing clock detector (mcd) is a one-shot circuit th at is triggered by the system clock. if the system clock remains high or low for more than the mcd timeout, t he one-shot will time ou t and generate a reset. after a mcd reset, the mcdrsf flag (rstsrc.2) will read 1, signifying the mcd as the reset source; oth- erwise, this bit reads 0. writing a 1 to the mcdrsf bit enables the mi ssing clock detector ; writing a 0 dis- ables it. the state of the rst pin is unaffected by this reset. sfr definition 25.1. vdm0cn: v dd monitor control bit7654321 0 name vdmen vddstat type r/wrrrrrr r reset varies varies varies varies varies varies varies varies bit name function 7vdmen v dd monitor enable. this bit turns the v dd monitor circuit on/off. the v dd monitor cannot generate sys- tem resets until it is also selected as a reset source in register rstsrc (sfr def- inition 25.2). selecting the v dd monitor as a reset source before it has stabilized may generate a system reset. in systems wher e this reset would be undesirable, a delay should be introduced between enabling the v dd monitor and selecting it as a reset source. 0: v dd monitor disabled. 1: v dd monitor enabled. 6vddstat v dd status. this bit indicates the current power supply status (v dd monitor output). 0: v dd is at or below the v dd monitor threshold. 1: v dd is above the v dd monitor threshold. 5:0 unused read = varies; write = don?t care. rev. 1.0 167 c8051f70x/71x 25.5. comparator0 reset comparator0 can be configured as a reset source by writing a 1 to the c0rsef flag (rstsrc.5). comparator0 should be enabled and allowed to settle prior to writing to c0rsef to prevent any turn-on chatter on the output from generating an unwanted rese t. the comparator0 reset is active-low: if the non- inverting input voltage (on cp0+) is less than the inverting input voltage (on cp0-), the device is put into the reset state. after a comparator0 reset, th e c0rsef flag (rstsrc.5) will read 1 signifying comparator0 as the reset source; otherwise, this bit reads 0. the state of the rst pin is unaffected by this reset. 25.6. watchdog timer reset the programmable watchdog timer (wdt) can be used to prevent software from running out of control during a system malfunction. the wdt function can be enabled or disabled by software as described in section ?26. watchdog timer? on pa ge 169. if a system malfunction preven ts user software from updating the wdt, a reset is generated and the wdtrsf bit (rstsrc.3) is set to 1. the state of the rst pin is unaffected by this reset. 25.7. flash error reset if a flash read/write/e rase or program read target s an illegal address, a system reset is generated. this may occur due to any of the following: ?? a flash write or erase is attempted above user code space. this occurs when pswe is set to 1 and a movx write operation targets an address above address 0x3dff. ?? a flash read is attempted above user code space. this occurs when a movc operation targets an address above address 0x3dff. ?? a program read is attempted above user code space. this occurs when user code attempts to branch to an address above 0x3dff. ?? a flash read, write or erase attempt is rest ricted due to a flash security setting (see section ?22.3. security options? on page 149 ). the ferror bit (rstsrc.6) is set following a flash error reset. the state of the rst pin is unaffected by this reset. 25.8. software reset software may force a reset by wr iting a 1 to the swrsf bit (rstsr c.4). the swrsf bit will read 1 fol- lowing a software forced reset. the state of the rst pin is unaffected by this reset. c8051f70x/71x 168 rev. 1.0 sfr address = 0xef; sfr page = all pages sfr definition 25.2. r stsrc: reset source bit76543210 name ferror c0rsef swrsf wdtrsf mcdrsf porsf pinrsf type r r r/w r/w r r/w r/w r reset 0 varies varies varies var ies varies varies varies bit name description write read 7 unused unused. don?t care. 0 6ferror flash error reset flag. n/a set to 1 if flash read/write/erase error caused the last reset. 5 c0rsef comparator0 reset enable and flag. writing a 1 enables comparator0 as a reset source (active-low). set to 1 if comparator0 caused the last reset. 4swrsf software reset force and flag. writing a 1 forces a sys- tem reset. set to 1 if last reset was caused by a write to swrsf. 3 wdtrsf watchdog timer reset flag. n/a set to 1 if watchdog timer overflow caused the last reset. 2 mcdrsf missing clock detector enable and flag. writing a 1 enables the missing clock detector. the mcd triggers a reset if a missing clock condition is detected. set to 1 if missing clock detector timeout caused the last reset. 1porsf power-on / v dd monitor reset flag, and v dd monitor reset enable. writing a 1 enables the v dd monitor as a reset source. writing 1 to this bit before the v dd monitor is enabled and stabilized may cause a system reset. set to 1 anytime a power- on or v dd monitor reset occurs. when set to 1 all other rstsrc flags are inde- terminate. 0pinrsf hw pin reset flag. n/a set to 1 if rst pin caused the last reset. note: do not use read-modify-write operations on this register rev. 1.0 169 c8051f70x/71x 26. watchdog timer the mcu includes a program mable watchdog timer (wdt ) running off the system clock. a wdt overflow will force the mcu into the rese t state. to prevent the reset, the wdt mu st be restarted by application soft- ware before overflow. if the system experiences a soft ware or hardware malfuncti on preventing the soft- ware from restarting the wdt, the wdt will overflow and cause a reset. following a reset the wdt is automatically enabled and running with the default maximum time interval. if desired the wdt can be disabled by system software or locked on to prevent accidental disabling. once locked, the wdt cannot be disabled until the next s ystem reset. the state of th e /rst pin is unaffected by this reset. the wdt consists of a 21-bit timer running from th e programmed system clock. the timer measures the period between specific writes to its control register. if this period exceeds the programmed limit, a wdt reset is generated. the wdt can be enabled and disabled as needed in software, or can be permanently enabled if desired. watchdog features are contro lled via the watchdog timer control register (wdtcn) shown in sfr definition 26.1. 26.1. enable/reset wdt the watchdog timer is both enabled and reset by writing 0xa5 to the wdtcn register. the user's applica- tion software should include periodic writes of 0x a5 to wdtcn as needed to prevent a watchdog timer overflow. the wdt is enabled and rese t as a result of any system reset. 26.2. disable wdt writing 0xde followed by 0xad to the wdtcn regi ster disables the wdt. the following code segment illustrates disabling the wdt: clr ea ; disable all interrupts mov wdtcn,#0deh ; disable software watchdog timer mov wdtcn,#0adh setb ea ; re-enable interrupts the writes of 0xde and 0xad must occur within 4 clo ck cycles of each other, or the disable operation is ignored. interrupts should be disabled during this procedure to avoid delay between the two writes. 26.3. disable wdt lockout writing 0xff to wdtcn locks out the disable feature. once locked out, the disable operation is ignored until the next system reset. writing 0xff does not enabl e or reset the watchdog timer. applications always intending to use the watchdog should writ e 0xff to wdtcn in the initialization code. 26.4. setting wdt interval wdtcn.[2:0] control the watchdog timeout interval. the interval is given by the following equation: 4^(3+wdtcn[2-0]) x tsysclk ;where t sysclk is the system clock period. for a 3 mhz system clock, this provides an interval range of 0.021 to 349.5 ms. wdtcn.7 must be logic 0 when setting this interval. read ing wdtcn returns the programmed interval. wdtcn.[2:0] reads 111b after a system reset. c8051f70x/71x 170 rev. 1.0 sfr address = 0xe3; sfr page = all pages sfr definition 26.1. wdtcn: watchdog timer control bit7654321 0 name wdt[7:0] type r/w reset 0001011 1 bit name description write read 7:0 wdt[7:0] wdt control. writing 0xa5 both enables and reloads the wdt. writing 0xde followed within 4 system clocks by 0xad disables the wdt. writing 0xff locks out the disable feature. 4 wdtstatus watchdog status bit. 0: wdt is inactive 1: wdt is active 2:0 wdttimeout watchdog timeout interval bits. wdtcn[2:0] bits set the watchdog timeout inter- val. when writing these bits, wdtcn[7] must be set to 0. rev. 1.0 171 c8051f70x/71x 27. oscillators and clock selection c8051f70x/71x devices include a prog rammable internal high-f requency oscillator and an external oscilla- tor drive circuit. the internal hi gh-frequency oscillator can be enabled /disabled and calib rated using the oscicn and oscicl registers, as shown in figure 27.1. the system clock can be sourced by the exter- nal oscillator circuit or the internal oscillator (default). the in ternal oscillator offers a selectable post-scaling feature, which is initially set to divide the clock by 8. figure 27.1. oscillator options 27.1. system clock selection the system clock source for the mcu can be select ed using the clksel register. the clock selected as the system clock can be divided by 1, 2, 4, 8, 16, 32, 64, or 128. when switching between two clock divide values, the transition may take up to 128 cycles of the undivided clock source. the clkrdy flag can be polled to determine when the new clock divide value has been applied. the clock divider must be set to "divide by 1" when entering suspend mode. the system clock source may also be switched on-the-fly. the switchover takes effect after one cl ock period of the slower oscillator. clock divider osc programmable internal clock generator input circuit en sysclk n oscicl oscicn ioscen ifrdy suspend stsync sse ifcn1 ifcn0 oscxcn xoscmd2 xoscmd1 xoscmd0 xfcn2 xfcn1 xfcn0 option 4 ? cmos mode xtal2 option 2 ? rc mode vdd xtal2 option 3 ? c mode xtal2 xtal1 xtal2 option 1 ? crystal mode 10m ? clksel clkdiv2 clkdiv1 clkdiv0 clkrdy clksl1 clksl0 clkrdy clock divider n c8051f70x/71x 172 rev. 1.0 sfr address = 0xbd; sfr page= f sfr definition 27.1. clksel: clock select bit7 6 543210 name clkrdy clkdiv[2:0] reserved clksel[2:0] type r r/w r/w r/w r r/w r/w r/w reset 0 0 000000 bit name function 7clkrdy system clock divider clock ready flag. 0: the selected clock divide setting has not been applied to the system clock. 1: the selected clock divide setting has been applied to the system clock. 6:4 clkdiv system clock divider bits. selects the clock division to be applied to the selected source (internal or external). 000: selected clock is divided by 1. 001: selected clock is divided by 2. 010: selected clock is divided by 4. 011: selected clock is divided by 8. 100: selected clock is divided by 16. 101: selected clock is divided by 32. 110: selected clock is divided by 64. 111: selected clock is divided by 128. 3 reserved read = 0b. must write 0b. 2:0 clksel[2:0] system clock select. selects the oscillator to be used as the undivided system clock source. 000: internal oscillator 001: external oscillator all other values reserved. rev. 1.0 173 c8051f70x/71x 27.2. programmable internal high-frequency (h-f) oscillator all c8051f70x/71x devices include a programmable internal hi gh-frequency oscillator that defaults as the system clock after a system reset. th e internal oscillator period can be adjusted via the oscicl register as defined by sfr definition 27.2. on c8051f70x/71x devices, osci cl is factory calibra ted to obtain a 24.5 mhz base frequency. the internal oscillator output frequency may be divided by 1, 2, 4, or 8, as defined by the ifcn bits in reg- ister oscicn. the divide value def aults to 8 following a reset. the precision oscillator supports a spread spectrum mode which modul ates the output frequency in order to reduce the emi generated by the system. when enabled (sse = 1) , the oscillator output frequency is modulated by a stepped triangle wave whose frequenc y is equal to the oscillato r frequency divided by 384 (63.8 khz using the factory calibration). the maximum dev iation from the center frequency is 0.75%. the output frequency updates occur every 32 cycles and th e step size is typically 0.25% of the center fre- quency. sfr address = 0xbf; sfr page = f sfr definition 27.2. oscicl: intern al h-f oscillator calibration bit76543210 name oscicl[6:0] type r/w reset varies varies varies varies varies varies varies varies bit name function 6:0 oscicl[7:0] internal oscillator calibration bits. these bits determine the internal oscillato r period. when set to 00000000b, the h-f oscillator operates at its fa stest setting. when set to 111 11111b, the h-f osc illator operates at its slowest setting. the reset value is factory calibrated to generate an internal oscillator frequency of 24.5 mhz. c8051f70x/71x 174 rev. 1.0 sfr address = 0xa9; sfr page = f sfr definition 27.3. oscicn: inte rnal h-f oscillator control bit76 5 43210 name ioscen ifrdy suspend stsync sse ifcn[1:0] type r/w r r/w r r/w r r/w reset 11 0 00000 bit name function 7ioscen internal h-f oscillator enable bit. 0: internal h-f oscillator disabled. 1: internal h-f oscillator enabled. 6ifrdy internal h-f oscillator frequency ready flag. 0: internal h-f oscillator is no t running at pr ogrammed frequency. 1: internal h-f oscillator is running at progr ammed frequency. 5 suspend internal oscillator suspend enable bit. setting this bit to logic 1 places the in ternal oscillator in suspend mode. the inter- nal oscillator resumes operation when one of the suspend mode awakening events occurs. 4 stsync suspend timer synchronization bit. this bit is used to indicate when it is sa fe to read and write the registers associated with the suspend wake-up timer. if a su spend wake-up source other than timer 3 has brought the oscillator out of suspend mode, it make ta ke up to three timer clocks before the timer can be read or written. 0: timer 3 registers can be read safely. 1: timer 3 register reads and writes should not be performed. 3sse spread spectrum enable. spread spectrum enable bit. 0: spread spectrum clock dithering disabled. 1: spread spectrum clock dithering enabled. 2 unused read = 0b; write = don?t care 1:0 ifcn[1:0] internal h-f oscillator fre quency divider control bits. 00: sysclk derived from internal h-f oscillator divided by 8. 01: sysclk derived from internal h-f oscillator divided by 4. 10: sysclk derived from internal h-f oscillator divided by 2. 11: sysclk derived from internal h-f oscillator divided by 1. rev. 1.0 175 c8051f70x/71x 27.3. external osci llator drive circuit the external oscillator circuit may drive an external cr ystal, ceramic resona tor, capacitor, or rc network. a cmos clock may also provide a clock input. for a cr ystal or ceramic resonator configuration, the crys- tal/resonator must be wired across the xtal1 and xt al2 pins as shown in op tion 1 of figure 27.1. a 10 m ?? resistor also must be wired across the xtal2 an d xtal1 pins for the crystal/resonator configura- tion. in rc, capacitor, or cmos clock configuration, the clock source should be wired to the xtal2 pin as shown in option 2, 3, or 4 of figure 27.1. the type of external oscillator must be selected in the oscxcn register, and the frequency control bits (xfcn) must be selected appropriately (see sfr definition 27.4). important note on external oscillator usage: port pins must be configured when using the external oscillator circuit. when the external oscillator drive ci rcuit is enabled in crystal /resonator mode, port pins p0.2 and p0.3 are used as xtal1 and xtal2 respectively. when the ex ternal oscillator drive circuit is enabled in capacitor, rc, or cmos clock mode, port pin p0.3 is used as xtal2. the port i/o crossbar should be configured to skip the port pins used by t he oscillator circuit; see sect ion ?28.3. priority crossbar decoder? on page 185 for crossbar configuration. additionally, when usin g the external oscillator circuit in crystal/resonator, capacitor, or rc mode, the associated port pins should be configured as analog inputs . in cmos clock mode, the associated pin should be configured as a digital input . see section ?28.4. port i/o initialization? on page 189 for deta ils on port inpu t mode selection. c8051f70x/71x 176 rev. 1.0 sfr address = 0xb5; sfr page = f sfr definition 27.4. oscxcn: ex ternal oscillator control bit76543210 name xtlvld xoscmd[2:0] xfcn[2:0] type rr/wrr/w reset 00000000 bit name function 7xtlvld crystal oscillator valid flag. (read only when xoscmd = 11x.) 0: crystal oscillator is u nused or not yet stable. 1: crystal oscillator is running and stable. 6:4 xoscmd[2:0] external oscillat or mode select. 00x: external oscillator circuit off. 010: external cmos clock mode. 011: external cmos clock mode with divide by 2 stage. 100: rc oscillator mode. 101: capacitor oscillator mode. 110: crystal oscillator mode. 111: crystal oscillator mode with divide by 2 stage. 3 unused read = 0; write = don?t care 2:0 xfcn[2:0] external oscillator frequency control bits. set according to the desired frequency for crystal or rc mode. set according to the desired k factor for c mode. xfcn crystal mode rc mode c mode 000 f ? 32 khz f ?? 25 khz k factor = 0.87 001 32 khz ?? f ?? 84 khz 25 khz ?? f ?? 50 khz k factor = 2.6 010 84 khz ? f ?? 225 khz 50 khz ?? f ?? 100 khz k factor = 7.7 011 225 khz ? f ?? 590khz 100khz ?? f ?? 200 khz k factor = 22 100 590 khz ? f ?? 1.5 mhz 200 khz ?? f ?? 400 khz k factor = 65 101 1.5 mhz ? f ?? 4mhz 400khz ?? f ?? 800 khz k factor = 180 110 4 mhz ? f ?? 10 mhz 800 khz ?? f ?? 1.6 mhz k factor = 664 111 10 mhz ? f ?? 30 mhz 1.6 mhz ?? f ?? 3.2 mhz k factor = 1590 rev. 1.0 177 c8051f70x/71x 27.3.1. external crystal example if a crystal or ceramic resonator is used as an external oscillator source for the mcu, the circuit should be configured as shown in figure 27.1, option 1. the external oscillato r frequency cont rol value (xfcn) should be chosen from the crystal column of the ta ble in sfr definition 27.4 (oscxcn register). for example, an 11.0592 mhz crystal requires an xfcn setting of 111b and a 32.768 khz watch crystal requires an xfcn setting of 001b. after an external 32.768 khz oscillator is st abilized, the xfcn setting can be switched to 000 to save power. it is recommended to enable the missing clock detector before switching the system clock to any external oscillator source. when the crystal oscillator is first enabled, the oscillator amplitude detec tion circuit requires a settling time to achieve proper bias. introduc ing a delay of 1 ms between enablin g the oscillator and checking the xtlvld bit will prevent a premature switch to the extern al oscillator as the system clock. switching to the external oscillator before the crysta l oscillator has stabilized can result in unpredictable behavior. the rec- ommended procedure is: 1. force xtal1 and xtal2 to a low state. this involv es enabling the crossbar and writing 0 to the port pins associated with xtal1 and xtal2. 2. configure xtal1 and xtal2 as analog inputs. 3. enable the external oscillator. 4. wait at least 1 ms. 5. poll for xtlvld = 1. 6. if desired, enable the missing clock detector. 7. switch the system clock to the external oscillator. important note on external crystals: crystal oscillator circuits are qui te sensitive to pcb layout. the crystal should be placed as close as possible to th e xtal pins on the device. the traces should be as short as possible and shielded with ground plane fr om any other traces whic h could introduce noise or interference. the capacitors shown in the external crystal configur ation provide the load capacitance required by the crystal for correct oscillation. these capacitors are "in series" as seen by the crystal and "in parallel" with the stray capacitance of the xtal1 and xtal2 pins. note: the desired load capacitance depends upon the crystal and the manufacturer. please refer to the crystal data sheet when completing these calculations. for example, a tuning-fork crystal of 32.768 khz with a recommended load capacitance of 12.5 pf should use the configuration shown in figure 27.1, option 1. the total value of the capacitors and the stray capac- itance of the xtal pins should equal 25 pf. with a st ray capacitance of 3 pf per pin, the 22 pf capacitors yield an equivalent capacitance of 12.5 pf across the crystal, as shown in figure 27.2. c8051f70x/71x 178 rev. 1.0 figure 27.2. external 32.768 khz quartz crystal oscillator connection diagram 27.3.2. external rc example if an rc network is used as an external oscillator so urce for the mcu, the circ uit should be configured as shown in figure 27.1, option 2. the capacitor should be no greater than 100 pf; however for very small capacitors, the total capacitance may be dominated by parasitic capacitance in the pcb layout. to deter- mine the required external oscilla tor frequency control va lue (xfcn) in the oscxcn register, first select the rc network value to prod uce the desired frequency of oscilla tion, according to equation , where f = the frequency of oscillation in mhz, c = the capacitor value in pf, and r = the pull-up resistor value in k? . equation 27.1. rc mode oscillator frequency for example: if the frequency desired is 100 khz, let r = 246 k ? and c = 50 pf: f = 1.23( 10 3 ) / rc = 1.23 ( 10 3 ) / [ 246 x 50 ] = 0.1 mhz = 100 khz referring to the table in sfr definition 27.4, the required xfcn setting is 010b. xtal1 xtal2 10m ? 22pf* 22pf* 32.768 khz * capacitor values depend on crystal specifications f 1.23 10 3 ? rc ? ?? ? = rev. 1.0 179 c8051f70x/71x 27.3.3. external capacitor example if a capacitor is used as an external oscillator for t he mcu, the circuit should be configured as shown in figure 27.1, option 3. the capacitor should be no gr eater than 100 pf; however for very small capacitors, the total capacitance may be dominated by parasiti c capacitance in the pcb layout. to determine the required external oscillato r frequency control value (xfcn) in th e oscxcn register, select the capaci- tor to be used and find the frequen cy of oscillation according to equati on , where f = the frequency of oscil- lation in mhz, c = the ca pacitor value in pf, and v dd = the mcu power supply in volts. equation 27.2. c mode oscillator frequency for example: assume v dd = 3.0 v and f = 150 khz: f = kf / (c x vdd) 0.150 mhz = kf / (c x 3.0) since the frequency of roughly 150 khz is desired, select the k factor from the table in sfr definition 27.4 (oscxcn) as kf = 22: 0.150 mhz = 22 / (c x 3.0) c x 3.0 = 22 / 0.150 mhz c = 146.6 / 3.0 pf = 48.8 pf therefore, the xfcn value to use in this example is 011b and c = 50 pf. fkf ?? rv dd ? ?? ? = c8051f70x/71x 180 rev. 1.0 28. port input/output digital and analog resources are available through 64 i/o pins. each of the port pins p0.0?p2.7 can be defined as general-purpose i/o (gpio), assigned to one of the internal digital resources, or assigned to an analog function as shown in figure 28.4. the designe r has complete control over which functions are assigned, limited only by th e number of physical i/o pins. this re source assignment flexibility is achieved through the use of a priority crossbar decoder. the stat e of a port i/o pin can always be read in the corre- sponding port latch, regardless of the crossbar settings. the crossbar assigns the selected internal digital re sources to the i/o pins based on the priority decoder. the registers xbr0 and xbr1, defined in sfr definition 28.1 and sfr definition 28.2, are used to select internal digital functions. all port i/os except p0.3 are tolerant of voltages up to 2 v above the v dd supply (refer to figure 28.2 for the port cell circuit). the port i/o cells are configured as either push-pull or open-drain in the port output mode registers (pnmdout, where n = 0,1). complete el ectrical specifications for port i/o are given in section ?9. electrical char acteristics? on page 47. figure 28.1. port i/o functional block diagram xbr0, xbr1, pnskip registers digital crossbar priority decoder 2 p0 i/o cells p0.0 p0.7 8 port match p0mask, p0mat p1mask, p1mat uart (internal digital signals) highest priority lowest priority sysclk 2 smbus t0, t1 2 4 pca 2 cp0 outputs spi 4 p1.0 8 (port latches) p0 (p0.0-p0.7) (p1.0-p1.7) 8 8 p1 8 pnmdout, pnmdin , pndrv registers p1.7 p2.0 p2.7 to analog peripherals (adc0, cp0, vref, xtal) external interrupts ex0 and ex1 p1 i/o cells p2 i/o cells p3 i/o cells p4 i/o cells p5 i/o cells p6 i/o cells p3.0 p3.7 p4.0 p4.7 p5.0 p5.7 p6.0 p6.5 to cs0 rev. 1.0 181 c8051f70x/71x 28.1. port i/o m odes of operation port pins p0.0 - p6.5 use the port i/o cell shown in figure 28.2. each port i/o cell can be configured by software for analog i/o or digital i/o using the pnmdin registers. on rese t, all port i/o ce lls default to a high impedance state with weak pull-ups enabled. until the crossbar is enabled (xbare = 1), both the high and low port i/o drive circuits are explicitly disabled on all crossbar pins. 28.1.1. port pins conf igured for analog i/o any pins to be used as comparator or adc input, capa citive sense input, external oscillator input/output, vref output, or agnd connection should be configured for analog i/o (pnmdin.n = 0). when a pin is configured for analog i/o, its weak pullup, digital driver , and digital receiver are disabled. port pins config- ured for analog i/o will alwa ys read back a value of 0. configuring pins as analog i/o saves power and isolates the port pin from digital interference. port pins configured as digital i/o may still be used by analog pe ripherals; however, this practice is not recom- mended and may result in measurement errors. 28.1.2. port pins configured for digital i/o any pins to be used by digital peripherals (uart, spi, smbus, etc.), external event trigger functions, or as gpio should be configured as digital i/o (pnmdin.n = 1). for digital i/o pins, one of two output modes (push-pull or open-drain) must be selected using the pnmdout registers. push-pull outputs (pnmdout.n = 1) drive the port pad to the vdd or gnd supply rails based on the out- put logic value of the port pin. open-drain outputs have the high side driver disabled; therefore, they only drive the port pad to gnd when the output logic va lue is 0 and become high impedance inputs (both high low drivers turned off) when the output logic value is 1. when a digital i/o cell is placed in the high impedance state, a weak pull-up transistor pulls the port pad to the vdd supply voltage to ensure th e digital input is at a defined logic state. weak pull-ups are disabled when the i/o cell is driven to gnd to minimize powe r consumption, and they may be globally disabled by setting weakpud to 1. the user should ensure that digita l i/o are always internally or externally pulled or driven to a valid logic state to minimize power consum ption. port pins configured for digital i/o always read back the logic state of the port pad, regardless of the output logic value of the port pin. figure 28.2. port i/o cell block diagram gnd vdd vdd (weak) port pad to/from analog peripheral pxmdin.x (1 for digital) (0 for analog) px.x ? output logic value (port latch or crossbar) xbare (crossbar enable) px.x ? input logic value (reads 0 when pin is configured as an analog i/o) pxmdout.x (1 for push-pull) (0 for open-drain) weakpud (weak pull-up disable) c8051f70x/71x 182 rev. 1.0 28.1.3. interfacing port i/o to 5 v logic all port i/o configured for digital, open-drain operatio n are capable of interfacing to digital logic operating at a supply voltage up to 2 v higher than vdd and less than 5.25 v. an external pull-up resistor to the higher supply voltage is typically required for most systems. important note: in a multi-voltage interface, the external pull-up resistor should be sized to allow a current of at least 150 a to flow into the port pin wh en the supply voltage is between (vdd + 0. 6v) and (vdd + 1.0v). once the port pin voltage increases beyond this range, the current flowing into the port pin is minimal. figure 28.3 shows the inpu t current characteristics of port pins driven above vdd. the port pin requires 150 a peak overdrive current when its voltage reaches approximately (vdd + 0.7 v). figure 28.3. port i/o overdrive current 28.1.4. increasing port i/o drive strength port i/o output drivers support a high and low drive st rength; the default is low drive strength. the drive strength of a port i/o can be configured using the pn drv registers. see section ?9. electrical characteris- tics? on page 47 for the difference in output drive strength between the two modes. 28.2. assigning port i/o pins to analog and digital functions port i/o pins p0.0?p2.7 can be assigned to various a nalog, digital, and external interrupt functions. the port pins assigned to analog functions should be config ured for analog i/o, and port pins assigned to digi- tal or external interrupt functions should be configured for digital i/o. 28.2.1. assigning port i/o pins to analog functions table 28.1 shows all available analog func tions that require port i/o assignments. port pins selected for these analog functions should have their corresponding bit in pnskip set to 1. this reserves the pin for use by the analog function and do es not allow it to be claimed by the crossbar. table 28.1 shows the potential mapping of port i/o to each analog function. + - v test i vtest v dd i vtest (a) v test (v) 0 -10 -150 v dd v dd +0.7 i/o cell port i/o overdrive current vs. voltage port i/o overdrive test circuit rev. 1.0 183 c8051f70x/71x table 28.1. port i/o assignment for analog functions analog function potentially assignable port pins sfr(s) used for assignment adc input p0.0?p1.7 amx0p, amx0n, pnskip, pnmdin comparator0 input p1.0?p1.7 cpt0mx, pnskip, pnmdin cs0 input p2.0?p6.5 pnmdin voltage reference (vref0) p0.0 ref0cn, p0skip, pnmdin ground reference (agnd) p0.1 ref0cn, p0skip external oscillator in crystal m ode (xtal1) p0.2 oscxcn, p0skip, p0mdin external oscillator in rc, c, or cr ystal mode (xtal2) p0.3 oscxcn, p0skip, p0mdin c8051f70x/71x 184 rev. 1.0 28.2.2. assigning port i/o pins to digital functions any port pins not assigned to analog functions may be assigned to digital functions or used as gpio. most digital functions rely on the crossbar for pin assi gnment; however, some digital functions bypass the crossbar in a manner similar to the analog functions listed above. port pins used by these digital func- tions and any port pins selected for use as gpio should have their corresponding bit in pnskip set to 1. table 28.2 shows all available digital functions and th e potential mapping of port i/o to each digital function. 28.2.3. assigning port i/o pins to external event trigger functions external event trigger functions can be used to trigger an interrupt or wake the device from a low power mode when a transition occurs on a digital i/o pin. the event trigger functions do not require dedicated pins and will function on both gpio pins (pnskip = 1) and pins in use by the crossbar (pnskip = 0). external event trigger functions cannot be used on pi ns configured for analog i/o. table 28.3 shows all available external event trigger functions. table 28.2. port i/o assignment for digital functions digital function potentially assignable port pins sfr(s) used for assignment uart0, spi0, smbus, cp0, cp0a, sysclk, pca0 (cex0-2 and eci), t0 or t1. any port pin available for assignment by the crossbar. this includes p0.0?p2.7 pins which have their pnskip bit set to 0. note: the crossbar will always assign uart0 pins to p0.4 and p0.5. xbr0, xbr1 any pin used for gpio p0.0?p6.5 p0skip, p1skip, p2skip external memory inte rface p3.0?p6.2 emi0cf table 28.3. port i/o assignment for external event trigger functions event trigger function potentially assignable port pins sfr(s) used for assignment external interrup t 0 p0.0?p0.7 it01cf external interrup t 1 p0.0?p0.7 it01cf port match p0.0?p1.7 p0mask, p0mat p1mask, p1mat rev. 1.0 185 c8051f70x/71x 28.3. priority crossbar decoder the priority crossbar decoder assigns a priority to each i/o function, starting at the top with uart0. when a digital resource is selected, the l east-significant unassigned port pin is assigned to that resource (exclud- ing uart0, which is always at pins 4 and 5). if a po rt pin is assigned, the crossbar skips that pin when assigning the next selected resource. the potential crossbar pin assignments are shown in figure 28.4. additionally, the crossbar will skip port pins whose a ssociated bits in the pn skip registers are set. the pnskip registers allow software to skip port pins that are to be us ed for analog input, dedicated functions, or gpio. the crossbar skips selected pins as if they were already assigned, and moves to the next unas- signed pin. figure 28.5 shows an example crossbar co nfiguration with no pins skipped. figure 28.6 shows the same example with pins p0.2, p0.3 and p1.0 skipped. if a port pin is claimed by a peripheral without use of the crossbar, its corresponding pnskip bit should be set. this applies to p0.0 if vref is used, p0.1 if agnd is used, p0.3 and/or p0.2 if the external oscillator circuit is enabled, p0.6 if the adc is configured to use the external conversion start signal (cnvstr), and any selected adc or comparator inputs. it is also important to skip any pins that do not exist for the pack- age being used. registers xbr0 and xbr1 are used to assign the digital i/o resources to the physical i/o port pins. when the smbus is selected, the crossbar assigns both pi ns associated with the smbus (sda and scl); when the uart is selected, the crossbar assigns both pins associated with the uart (tx and rx). uart0 pin assignments are fixed for bootloading purposes: ua rt tx0 is always assigned to p0.4; uart rx0 is always assigned to p0.5. standard port i/os appear co ntiguously after the priori tized functions have been assigned. important note: the spi can be operated in either 3-wire or 4-wire modes, pending the state of the nssmd1?nssmd0 bits in register spi0cn. according to the spi mode, the nss signal may or may not be routed to a port pin. c8051f70x/71x 186 rev. 1.0 figure 28.4. crossbar priority decoder?possible pin assignments tx0 rx0 sda scl cp0 cp0a sysclk cex0 cex1 cex2 eci t0 t1 0 1 2 3 4 5 6 7 p0 port pin number special function signals vref xtal2 cnvstr 0 0 0 0 0 0 0 0 p0skip pin skip settings agnd xtal1 sck miso mosi nss* 0 1 2 3 4 5 6 7 p1 0 0 0 0 0 0 0 0 p1skip 0 1 2 3 4 5 6 7 p2 0 0 0 0 0 0 0 0 p2skip the crossbar peripherals are assigned in priority order from top to bottom, according to this diagram. these boxes represent port pins wh ich can potentially be as signed to a peripheral. special function signals are not as signed by the crossbar. when these signals are enabled, the crossbar should be manually config ured to skip the corresponding port pins. pins can be ?skipped? by se tting the corresponding bit in pnskip to 1. * nss is only pinned out when the spi is in 4-wire mode. rev. 1.0 187 c8051f70x/71x figure 28.5. crossbar priority decoder in example configuration?no pins skipped tx0 rx0 sda scl cp0 cp0a sysclk cex0 cex1 cex2 eci t0 t1 0 1 2 3 4 5 6 7 p0 port pin number special function signals vref xtal2 cnvstr 0 0 0 0 0 0 0 0 p0skip pin skip settings agnd xtal1 sck miso mosi nss* 0 1 2 3 4 5 6 7 p1 0 0 0 0 0 0 0 0 p1skip 0 1 2 3 4 5 6 7 p2 0 0 0 0 0 0 0 0 p2skip tx0 and rx0 are fixed at these locations the other peripherals are assigned based on pin availability, in priority order. this example shows a crossbar configuration with xbr0 = 0x07 and xbr1 = 0x43. these boxes represent port pi ns which are assigned to a peripheral. c8051f70x/71x 188 rev. 1.0 figure 28.6. crossbar priority decoder in example configuration?3 pins skipped tx0 rx0 sda scl cp0 cp0a sysclk cex0 cex1 cex2 eci t0 t1 0 1 2 3 4 5 6 7 p0 port pin number special function signals vref xtal2 cnvstr 0 0 1 1 0 0 0 0 p0skip pin skip settings agnd xtal1 sck miso mosi nss* 0 1 2 3 4 5 6 7 p1 1 0 0 0 0 0 0 0 p1skip 0 1 2 3 4 5 6 7 p2 0 0 0 0 0 0 0 0 p2skip this example shows a crossbar configuration with xbr0 = 0x07 and xbr1 = 0x43. these boxes represent port pins which are assigned to a peripheral. p0.2 skipped p0.3 skipped p1.0 skipped if a pin is skipped, it is not available for assignment, and the crossbar will move the assignment to the next available pin rev. 1.0 189 c8051f70x/71x 28.4. port i/o initialization port i/o initialization cons ists of the following steps: 1. select the input mode (analog or digital) for all port pins, using the port input mode register (pnmdin). 2. select the output mode (open-drain or push-pull) fo r all port pins, using the port output mode register (pnmdout). 3. select any pins to be skipped by the i/o cr ossbar using the port skip registers (pnskip). 4. assign port pins to desired peripherals. 5. enable the cro ssbar (xbare = 1). all port pins must be configured as either analog or digital inputs. any pins to be used as comparator or adc inputs should be configured as an analog inputs. when a pin is configured as an analog input, its weak pullup, digital driver, and digital receiver are disabled. this process saves power and reduces noise on the analog input. pins configured as digital inputs may still be used by analog peripherals; however this practice is not recommended. additionally, all analog input pins should be config ured to be skipped by the crossbar (accomplished by setting the associated bits in pnskip). port input mode is set in the pnmdin register, where a 1 indicates a digital input, and a 0 indicates an analog input. all pins default to digital inputs on reset. see sfr definition 28.8 for the pnmdin register details. the output driver characteristics of the i/o pins ar e defined using the port output mode registers (pnmd- out). each port output driver can be configured as either open drain or pus h-pull. this selection is required even for the digital resources selected in the xbrn registers, and is not automatic. the only exception to this is the smbus (sda, scl) pins, which are configured as open-drain regardless of the pnmdout settings. when the weakpud bit in xbr1 is 0, a weak pullup is enabled for all po rt i/o config- ured as open-drain. weakpu d does not affect the pu sh-pull port i/o. furthe rmore, the weak pullup is turned off on an output that is driving a 0 to avoid unnecessary power dissipation. registers xbr0 and xbr1 must be loaded with the approp riate values to select the digital i/o functions required by the design. setting the xbare bit in xbr1 to 1 enables the crossbar. until the crossbar is enabled, the external pins remain as standard port i/o (in input mode), regardless of the xbrn register settings. for given xbrn register settings, one can de termine the i/o pin-out using the priority decode table; as an alternative, the confi guration wizard utility of the silicon labs ide software will determine the port i/o pin-assignments based on the xbrn register settings. the crossbar must be enabled to us e port pins as standard port i/o in output mode. port output drivers are disabled while the crossbar is disabled. c8051f70x/71x 190 rev. 1.0 sfr address = 0xe1; sfr page = f sfr definition 28.1. xbr0: port i/o crossbar register 0 bit76543210 name cp0ae cp0e syscke smb0e spi0e urt0e type r r r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:6 unused read = 00b; write = don?t care. 5cp0ae comparator0 asynchronous output enable. 0: asynchronous cp0 unavailable at port pin. 1: asynchronous cp0 routed to port pin. 4cp0e comparator0 output enable. 0: cp0 unavailable at port pin. 1: cp0 routed to port pin. 3 syscke sysclk output enable. 0: sysclk unavailable at port pin. 1: sysclk output routed to port pin. 2smb0e smbus i/o enable. 0: smbus i/o unavailable at port pins. 1: smbus i/o routed to port pins. 1spi0e spi i/o enable. 0: spi i/o unavailable at port pins. 1: spi i/o routed to port pins. note that the spi can be assigned either 3 or 4 gpio pins. 0urt0e uart i/o output enable. 0: uart i/o unavailable at port pin. 1: uart tx0, rx0 routed to port pins p0.4 and p0.5. rev. 1.0 191 c8051f70x/71x sfr address = 0xe2; sfr page = f sfr definition 28.2. xbr1: port i/o crossbar register 1 bit7 6543210 name weakpud xbare t1e t0e ecie pca0me[1:0] type r/w r/w r/w r/w r/w r r/w r/w reset 0 0000000 bit name function 7 weakpud port i/o weak pullup disable. 0: weak pullups enabled (except for ports whose i/o are configured for analog mode). 1: weak pullups disabled. 6 xbare crossbar enable. 0: crossbar disabled. 1: crossbar enabled. 5t1e t1 enable. 0: t1 unavailable at port pin. 1: t1 routed to port pin. 4t0e t0 enable. 0: t0 unavailable at port pin. 1: t0 routed to port pin. 3ecie pca0 external counter input enable. 0: eci unavailable at port pin. 1: eci routed to port pin. 2 unused read = 0b; write = don?t care. 1:0 pca0me[1:0] pca module i/o enable bits. 00: all pca i/o unavailable at port pins. 01: cex0 routed to port pin. 10: cex0, cex1 routed to port pins. 11: cex0, cex1, cex2 routed to port pins. c8051f70x/71x 192 rev. 1.0 28.5. port match port match functionality allows system events to be tr iggered by a logic value change on p0 or p1. a soft- ware controlled value stored in the pnmatch registers specifies the expected or normal logic values of p0 and p1. a port mismatch event occurs if the logic levels of the port?s input pins no longer match the soft- ware controlled value. this allows software to be notified if a certain change or pattern occurs on p0 or p1 input pins regardless of the xbrn settings. the pnmask registers can be used to individually select which p0 and p1 pins should be compared against the pnmatch regist ers. a port mismatch event is gene rated if (p0 & p0m ask) does not equal (p0match & p0mask) or if (p1 & p1mask) does not equal (p1match & p1mask). a port mismatch event may be used to generate an interrupt or wake the device from a low power mode, such as idle or suspend. see the interrupts and power options chapters for more details on interrupt and wake-up sources. sfr address = 0xf4; sfr page = 0 sfr definition 28.3. p0mask: port 0 mask register bit76543210 name p0mask[7:0] type r/w reset 00000000 bit name function 7:0 p0mask[7:0] port 0 mask value. selects p0 pins to be compared to the corresponding bits in p0mat. 0: p0.n pin logic value is ignored an d cannot cause a port mismatch event. 1: p0.n pin logic value is compared to p0mat.n. rev. 1.0 193 c8051f70x/71x sfr address = 0xf3; sfr page = 0 sfr address = 0xe2; sfr page = 0 sfr definition 28.4. p0mat: port 0 match register bit76543210 name p0mat[7:0] type r/w reset 11111111 bit name function 7:0 p0mat[7:0] port 0 match value. match comparison value used on port 0 for bits in p0mask which are set to 1. 0: p0.n pin logic value is compared with logic low. 1: p0.n pin logic value is compared with logic high. sfr definition 28.5. p1mask: port 1 mask register bit76543210 name p1mask[7:0] type r/w reset 00000000 bit name function 7:0 p1mask[7:0] port 1 mask value. selects p1 pins to be compared to the corresponding bits in p1mat. 0: p1.n pin logic value is ignored an d cannot cause a port mismatch event. 1: p1.n pin logic value is compared to p1mat.n. c8051f70x/71x 194 rev. 1.0 sfr address = 0xe1; sfr page = 0 28.6. special function re gisters for accessing an d configuring port i/o all port i/o are accessed through corresponding spec ial function registers (sfrs) that are both byte addressable and bit addressable. when writing to a port, the value writt en to the sfr is latched to main- tain the output data value at each pin. when reading, the logic levels of the port's input pins are returned regardless of the xbrn settings (i.e., even when the pin is assigned to another signal by the crossbar, the port register can always read its corresponding port i/ o pin). the exception to this is the execution of the read-modify-write instructio ns that target a port latch register as the destination. the read-modify-write instructions when operating on a port sfr are the fo llowing: anl, orl, xrl, jbc, cpl, inc, dec, djnz and mov, clr or setb, when the destination is an indi vidual bit in a port sfr. for these instructions, the value of the latch register (not the pin) is read, modified, and written back to the sfr. each port has a corresponding pnskip register which allo ws its individual port pins to be assigned to dig- ital functions or skipped by the crossbar. all port pins used for analog functions, gpio, or dedicated digital functions such as the emif shou ld have their pnskip bit set to 1. the port input mode of the i/o pins is defined using the port input mode registers (pnmdin). each port cell can be configured for analog or digital i/o. this selection is required even for the digital resources selected in the xbrn registers, and is not automatic. the output driver characteristics of the i/o pins ar e defined using the port output mode registers (pnmd- out). each port output driver can be configured as either open drain or pus h-pull. this selection is required even for the digital resources selected in the xbrn registers, and is not automatic. the only exception to this is the smbus (sda, scl) pins, which are configured as open-drain regardless of the pnmdout settings. sfr definition 28.6. p1mat: port 1 match register bit76543210 name p1mat[7:0] type r/w reset 11111111 bit name function 7:0 p1mat[7:0] port 1 match value. match comparison value used on port 1 for bits in p1mask which are set to 1. 0: p1.n pin logic value is compared with logic low. 1: p1.n pin logic value is compared with logic high. rev. 1.0 195 c8051f70x/71x sfr address = 0x80; sfr page = all pages; bit addressable sfr address = 0xf1; sfr page = f sfr definition 28.7. p0: port 0 bit76543210 name p0[7:0] type r/w reset 11111111 bit name description write read 7:0 p0[7:0] port 0 data. sets the port latch logic value or reads the port pin logic state in port cells con- figured for digital i/o. 0: set output latch to logic low. 1: set output latch to logic high. 0: p0.n port pin is logic low. 1: p0.n port pin is logic high. sfr definition 28.8. p0mdi n: port 0 input mode bit76543210 name p0mdin[7:0] type r/w reset 11111111 bit name function 7:0 p0mdin[7:0] analog configuration bits for p0.7?p0.0 (respectively). port pins configured for analog mode ha ve their weak pullup, digital driver, and digital receiver disabled. 0: corresponding p0.n pin is configured for analog mode. 1: corresponding p0.n pin is not configured for analog mode. c8051f70x/71x 196 rev. 1.0 sfr address = 0xa4; sfr page = f sfr address = 0xd4; sfr page = f sfr definition 28.9. p0mdo ut: port 0 output mode bit76543210 name p0mdout[7:0] type r/w reset 00000000 bit name function 7:0 p0mdout[7:0] output configuration bits for p0.7?p0.0 (respectively). these bits are ignored if the correspondi ng bit in register p0mdin is logic 0. 0: corresponding p0.n output is open-drain. 1: corresponding p0.n output is push-pull. sfr definition 28.10. p0skip: port 0 skip bit76543210 name p0skip[7:0] type r/w reset 00000000 bit name function 7:0 p0skip[7:0] port 0 crossbar skip enable bits. these bits select port 0 pins to be skip ped by the crossbar decoder. port pins used for analog, special functions or gpio should be skipped by the crossbar. 0: corresponding p0.n pin is not skipped by the crossbar. 1: corresponding p0.n pin is skipped by the crossbar. rev. 1.0 197 c8051f70x/71x sfr address = 0xf9; sfr page = f sfr address = 0x90; sfr page = all pages; bit addressable sfr definition 28.11. p0drv: port 0 drive strength bit76543210 name p0drv[7:0] type r/w reset 00000000 bit name function 7:0 p0drv[7:0] drive strength configuration bits for p0.7?p0.0 (respectively). configures digital i/o port cells to high or low output drive strength. 0: corresponding p0.n output has low output drive strength. 1: corresponding p0.n output has high output drive strength. sfr definition 28.12. p1: port 1 bit76543210 name p1[7:0] type r/w reset 11111111 bit name description write read 7:0 p1[7:0] port 1 data. sets the port latch logic value or reads the port pin logic state in port cells con- figured for digital i/o. 0: set output latch to logic low. 1: set output latch to logic high. 0: p1.n port pin is logic low. 1: p1.n port pin is logic high. c8051f70x/71x 198 rev. 1.0 sfr address = 0xf2; sfr page = f sfr address = 0xa5; sfr page = f sfr definition 28.13. p1mdin: port 1 input mode bit76543210 name p1mdin[7:0] type r/w reset 1*1111111 bit name function 7:0 p1mdin[7:0] analog configuration bits for p1.7?p1.0 (respectively). port pins configured for analog mode ha ve their weak pullup, digital driver, and digital receiver disabled. 0: corresponding p1.n pin is configured for analog mode. 1: corresponding p1.n pin is not configured for analog mode. note: on c8051f716 and c8051f717 devices, p1.7 will default to analog mode. if the p1mdin register is written on the c8051f716 and c8051f717 devices, p1.7 should always be configured as analog. sfr definition 28.14. p1mdout: port 1 output mode bit76543210 name p1mdout[7:0] type r/w reset 00000000 bit name function 7:0 p1mdout[7:0] output configuration bits for p1.7?p1.0 (respectively). these bits are ignored if the correspondi ng bit in register p1mdin is logic 0. 0: corresponding p1.n output is open-drain. 1: corresponding p1.n output is push-pull. rev. 1.0 199 c8051f70x/71x sfr address = 0xd5; sfr page = f sfr address = 0xfa; sfr page = f sfr definition 28.15. p1skip: port 1 skip bit76543210 name p1skip[7:0] type r/w reset 00000000 bit name function 7:0 p1skip[7:0] port 1 crossbar skip enable bits. these bits select port 1 pins to be skip ped by the crossbar decoder. port pins used for analog, special functions or gpio should be skipped by the crossbar. 0: corresponding p1.n pin is not skipped by the crossbar. 1: corresponding p1.n pin is skipped by the crossbar. sfr definition 28.16. p1drv: port 1 drive strength bit76543210 name p1drv[7:0] type r/w reset 00000000 bit name function 7:0 p1drv[7:0] drive strength configuration bits for p1.7?p1.0 (respectively). configures digital i/o port cells to high or low output drive strength. 0: corresponding p1.n output has low output drive strength. 1: corresponding p1.n output has high output drive strength. c8051f70x/71x 200 rev. 1.0 sfr address = 0xa0; sfr page = all pages; bit addressable sfr address = 0xf3; sfr page = f sfr definition 28.17. p2: port 2 bit76543210 name p2[7:0] type r/w reset 11111111 bit name description write read 7:0 p2[7:0] port 2 data. sets the port latch logic value or reads the port pin logic state in port cells con- figured for digital i/o. 0: set output latch to logic low. 1: set output latch to logic high. 0: p2.n port pin is logic low. 1: p2.n port pin is logic high. sfr definition 28.18. p2mdin: port 2 input mode bit76543210 name p2mdin[7:0] type r/w reset 11111111 bit name function 7:0 p2mdin[7:0] analog configuration bits for p2.7?p2.0 (respectively). port pins configured for analog mode ha ve their weak pullup, digital driver, and digital receiver disabled. 0: corresponding p2.n pin is configured for analog mode. 1: corresponding p2.n pin is not configured for analog mode. rev. 1.0 201 c8051f70x/71x sfr address = 0xa6; sfr page = f sfr address = 0xd6; sfr page = f sfr definition 28.19. p2mdout: port 2 output mode bit76543210 name p2mdout[7:0] type r/w reset 00000000 bit name function 7:0 p2mdout[7:0] output configuration bits for p2.7?p2.0 (respectively). these bits are ignored if the correspondi ng bit in register p2mdin is logic 0. 0: corresponding p2.n output is open-drain. 1: corresponding p2.n output is push-pull. sfr definition 28.20. p2skip: port 2 skip bit76543210 name p2skip[7:0] type r/w reset 00000000 bit name function 7:0 p2skip[3:0] port 2 crossbar skip enable bits. these bits select port 2 pins to be skip ped by the crossbar decoder. port pins used for analog, special functions or gpio should be skipped by the crossbar. 0: corresponding p2.n pin is not skipped by the crossbar. 1: corresponding p2.n pin is skipped by the crossbar. c8051f70x/71x 202 rev. 1.0 sfr address = 0xfb; sfr page = f sfr address = 0xb0; sfr page = all pages; bit addressable sfr definition 28.21. p2drv: port 2 drive strength bit76543210 name p2drv[7:0] type r/w reset 00000000 bit name function 7:0 p2drv[7:0] drive strength configuration bits for p2.7?p2.0 (respectively). configures digital i/o port cells to high or low output drive strength. 0: corresponding p2.n output has low output drive strength. 1: corresponding p2.n output has high output drive strength. sfr definition 28.22. p3: port 3 bit76543210 name p3[7:0] type r/w reset 11111111 bit name description write read 7:0 p3[7:0] port 3 data. sets the port latch logic value or reads the port pin logic state in port cells con- figured for digital i/o. 0: set output latch to logic low. 1: set output latch to logic high. 0: p3.n port pin is logic low. 1: p3.n port pin is logic high. rev. 1.0 203 c8051f70x/71x sfr address = 0xf4; sfr page = f sfr address = 0xaf; sfr page = f sfr definition 28.23. p3mdin: port 3 input mode bit76543210 name p3mdin[7:0] type r/w reset 11111111 bit name function 7:0 p3mdin[7:0] analog configuration bits for p3.7?p3.0 (respectively). port pins configured for analog mode ha ve their weak pullup, digital driver, and digital receiver disabled. 0: corresponding p3.n pin is configured for analog mode. 1: corresponding p3.n pin is not configured for analog mode. sfr definition 28.24. p3mdout: port 3 output mode bit76543210 name p3mdout[7:0] type r/w reset 00000000 bit name function 7:0 p3mdout[7:0] output configuration bits for p3.7?p3.0 (respectively). these bits are ignored if the correspondi ng bit in register p3mdin is logic 0. 0: corresponding p3.n output is open-drain. 1: corresponding p3.n output is push-pull. c8051f70x/71x 204 rev. 1.0 sfr address = 0xfc; sfr page = f sfr address = 0xac; sfr page = all pages sfr definition 28.25. p3drv: port 3 drive strength bit76543210 name p3drv[7:0] type r/w reset 00000000 bit name function 7:0 p3drv[7:0] drive strength configuration bits for p3.7-p3.0 (respectively). configures digital i/o port cells to high or low output drive strength. 0: corresponding p3.n output has low output drive strength. 1: corresponding p3.n output has high output drive strength. sfr definition 28.26. p4: port 4 bit76543210 name p4[7:0] type r/w reset 11111111 bit name description write read 7:0 p4[7:0] port 4 data. sets the port latch logic value or reads the port pin logic state in port cells con- figured for digital i/o. 0: set output latch to logic low. 1: set output latch to logic high. 0: p4.n port pin is logic low. 1: p4.n port pin is logic high. rev. 1.0 205 c8051f70x/71x sfr address = 0xf5; sfr page = f sfr address = 0x9a; sfr page = f sfr definition 28.27. p4mdin: port 4 input mode bit76543210 name p4mdin[7:0] type r/w reset 11111111 bit name function 7:0 p4mdin[7:0] analog configuration bits for p4.7?p4.0 (respectively). port pins configured for analog mode ha ve their weak pullup, digital driver, and digital receiver disabled. 0: corresponding p4.n pin is configured for analog mode. 1: corresponding p4.n pin is not configured for analog mode. sfr definition 28.28. p4mdout: port 4 output mode bit76543210 name p4mdout[7:0] type r/w reset 00000000 bit name function 7:0 p4mdout[7:0] output configuration bits for p4.7?p4.0 (respectively). these bits are ignored if the correspondi ng bit in register p4mdin is logic 0. 0: corresponding p4.n output is open-drain. 1: corresponding p4.n output is push-pull. c8051f70x/71x 206 rev. 1.0 sfr address = 0xfd; sfr page = f sfr address = 0xb3; sfr page = all pages sfr definition 28.29. p4drv: port 4 drive strength bit76543210 name p4drv[7:0] type r/w reset 00000000 bit name function 7:0 p4drv[7:0] drive strength configuration bits for p4.7?p4.0 (respectively). configures digital i/o port cells to high or low output drive strength. 0: corresponding p4.n output has low output drive strength. 1: corresponding p4.n output has high output drive strength. sfr definition 28.30. p5: port 5 bit76543210 name p5[7:0] type r/w reset 11111111 bit name description write read 7:0 p5[7:0] port 5 data. sets the port latch logic value or reads the port pin logic state in port cells con- figured for digital i/o. 0: set output latch to logic low. 1: set output latch to logic high. 0: p5.n port pin is logic low. 1: p5.n port pin is logic high. rev. 1.0 207 c8051f70x/71x sfr address = 0xf6; sfr page = f sfr address = 0x9b; sfr page = f sfr definition 28.31. p5mdin: port 5 input mode bit76543210 name p5mdin[7:0] type r/w reset 11111111 bit name function 7:0 p5mdin[7:0] analog configuration bits for p5.7?p5.0 (respectively). port pins configured for analog mode ha ve their weak pullup, digital driver, and digital receiver disabled. 0: corresponding p5.n pin is configured for analog mode. 1: corresponding p5.n pin is not configured for analog mode. sfr definition 28.32. p5mdout: port 5 output mode bit76543210 name p5mdout[7:0] type r/w reset 00000000 bit name function 7:0 p5mdout[7:0] output configuration bits for p5.7?p5.0 (respectively). these bits are ignored if the correspondi ng bit in register p5mdin is logic 0. 0: corresponding p5.n output is open-drain. 1: corresponding p5.n output is push-pull. c8051f70x/71x 208 rev. 1.0 sfr address = 0xfe; sfr page = f sfr address = 0xb2; sfr page = all pages sfr definition 28.33. p5drv: port 5 drive strength bit76543210 name p5drv[7:0] type r/w reset 00000000 bit name function 7:0 p5drv[7:0] drive strength configuration bits for p5.7?p5.0 (respectively). configures digital i/o port cells to high or low output drive strength. 0: corresponding p5.n output has low output drive strength. 1: corresponding p5.n output has high output drive strength. sfr definition 28.34. p6: port 6 bit76543210 name p6[5:0] type rr r/w reset 00111111 bit name description write read 7:6 unused read = 00b; write = don?t care 5:0 p6[5:0] port 6 data. sets the port latch logic value or reads the port pin logic state in port cells con- figured for digital i/o. 0: set output latch to logic low. 1: set output latch to logic high. 0: p6.n port pin is logic low. 1: p6.n port pin is logic high. rev. 1.0 209 c8051f70x/71x sfr address = 0xf7; sfr page = f sfr address = 0x9c; sfr page = f sfr definition 28.35. p6mdin: port 6 input mode bit76543210 name p6mdin[5:0] type rr r/w reset 00111111 bit name function 7:6 unused read = 00b; write = don?t care 5:0 p6mdin[5:0] analog configuration bits for p6.5?p6.0 (respectively). port pins configured for analog mode ha ve their weak pullup, digital driver, and digital receiver disabled. 0: corresponding p6.n pin is configured for analog mode. 1: corresponding p6.n pin is not configured for analog mode. sfr definition 28.36. p6mdout: port 6 output mode bit76543210 name p6mdout[5:0] type rr r/w reset 00000000 bit name function 7:6 unused read = 00b; write = don?t care 5:0 p6mdout[5:0] output configuration bits for p6.5?p6.0 (respectively). these bits are ignored if the correspondi ng bit in register p6mdin is logic 0. 0: corresponding p6.n output is open-drain. 1: corresponding p6.n output is push-pull. c8051f70x/71x 210 rev. 1.0 sfr address = 0xc1; sfr page = f sfr definition 28.37. p6drv: port 6 drive strength bit76543210 name p6drv[5:0] type rr r/w reset 00000000 bit name function 7:6 unused read = 00b; write = don?t care 5:0 p6drv[5:0] drive strength configuration bits for p6.5?p6.0 (respectively). configures digital i/o port cells to high or low output drive strength. 0: corresponding p6.n output has low output drive strength. 1: corresponding p6.n output has high output drive strength. rev. 1.0 211 c8051f70x/71x 29. cyclic redundancy check unit (crc0) c8051f70x/71x devices include a cyclic redundancy check unit (crc0) that can perform a crc using a 16-bit or 32-bit polynomial. crc0 accepts a stream of 8-bit data written to the crc0in register. crc0 posts the 16-bit or 32-bit result to an internal register. the internal result register may be accessed indi- rectly using the crc0pnt bits and crc0dat regist er, as shown in figure 29.1. crc0 also has a bit reverse register for quick data manipulation. figure 29.1. crc0 block diagram crc0in 8 crc0dat crc0cn crc0sel crc0init crc0val crc0pnt1 crc0pnt0 crc engine 4 to 1 mux result 32 8 8 8 8 8 crc0auto crc0cnt automatic crc controller flash memory 8 crc0flip write crc0flip read c8051f70x/71x 212 rev. 1.0 29.1. 16-bit crc algorithm the c8051f70x/71x crc unit calculates the 16-bit crc msb-first, using a poly of 0x1021. the following describes the 16-bit crc algorithm performed by the hardware: 1. xor the most-significant byte of th e current crc result with the input byte. if this is the first iteration of the crc unit, the curren t crc result will be the set in itial value (0x 0000 or 0xffff). 2. if the msb of the crc result is set, left-shift the crc result, and then xor the crc result with the polynomial (0x1021). 3. if the msb of the crc result is not set, left-shift the crc result. 4. repeat at step 2 for the number of input bits (8). for example, the 16-bit c8051f70x/71x crc algorithm can be described by the following code: unsigned short updatecrc (unsigned short crc_acc, unsigned char crc_input){ unsigned char i; // loop counter #define poly 0x1021 // create the crc "dividend" for polynomial arithmetic (binary arithmetic // with no carries) crc_acc = crc_acc ^ (crc_input << 8); // "divide" the poly into the dividend using crc xor subtraction // crc_acc holds the "remainder" of each divide // only complete this division for 8 bits since input is 1 byte for (i = 0; i < 8; i++) { // check if the msb is set (if msb is 1, then the poly can "divide" // into the "dividend") if ((crc_acc & 0x8000) == 0x8000) { // if so, shift the crc value, and xor "subtract" the poly crc_acc = crc_acc << 1; crc_acc ^= poly; } else { // if not, just shift the crc value crc_acc = crc_acc << 1; } } return crc_acc; // return the final remainder (crc value) } table 29.1 lists example input values and the associated outputs using the 16-bit c8051f70x/71x crc algorithm (an initial value of 0xffff is used): table 29.1. example 16-bit crc outputs input output 0x63 0xbd35 0xaa, 0xbb, 0xcc 0x6cf6 0x00, 0x00, 0xaa, 0xbb, 0xcc 0xb166 rev. 1.0 213 c8051f70x/71x 29.2. 32-bit crc algorithm the c8051f70x/71x crc unit calculates the 32-bit crc using a poly of 0x04c11db7. the crc-32 algo- rithm is "reflected", meaning that all of the input bytes and the final 32-bit output ar e bit-reversed in the pro- cessing engine. the following is a descr iption of a simplified crc algorith m that produces results identical to the hardware: 1. xor the least-significant byte of the current crc result with the input byte. if this is the first iteration of the crc unit, the current crc result will be the set initial value (0x00000000 or 0xffffffff). 2. right-shift the crc result. 3. if the lsb of the crc result is set, xor the cr c result with the reflected polynomial (0xedb88320). 4. repeat at step 2 for the number of input bits (8). for example, the 32-bit c8051f70x/71x crc algorithm can be described by the following code: unsigned long updatecrc (unsigned long crc_acc, unsigned char crc_input){ unsigned char i; // loop counter #define poly 0xedb88320 // bit-reversed version of the poly 0x04c11db7 // create the crc "dividend" for polynomial arithmetic (binary arithmetic // with no carries) crc_acc = crc_acc ^ crc_input; // "divide" the poly into the dividend using crc xor subtraction // crc_acc holds the "remainder" of each divide // only complete this division for 8 bits since input is 1 byte for (i = 0; i < 8; i++) { // check if the msb is set (if msb is 1, then the poly can "divide" // into the "dividend") if ((crc_acc & 0x00000001) == 0x00000001) { // if so, shift the crc value, and xor "subtract" the poly crc_acc = crc_acc >> 1; crc_acc ^= poly; } else { // if not, just shift the crc value crc_acc = crc_acc >> 1; } } return crc_acc; // return the final remainder (crc value) } table 29.2 lists example input values and the associated outputs using the 32-bit c8051f70x/71x crc algorithm (an initial value of 0xffffffff is used): table 29.2. example 32-bit crc outputs input output 0x63 0xf9462090 0xaa, 0xbb, 0xcc 0x41b207b3 0x00, 0x00, 0xaa, 0x bb, 0xcc 0x78d129bc c8051f70x/71x 214 rev. 1.0 29.3. preparing fo r a crc calculation to prepare crc0 for a crc calculati on, software should select the desired polynomial and set the initial value of the result. two polynomials are available: 0x1021 (16-bit) and 0x04c11db7 (32-bit). the crc0 result may be initialized to one of two values : 0x00000000 or 0xffffffff. the following steps can be used to initialize crc0. 1. select a polynomial (set crc0sel to 0 for 32-bit or 1 for 16-bit). 2. select the initial result value (set crc0 val to 0 for 0x000000 00 or 1 for 0xffffffff). 3. set the result to its initia l value (write 1 to crc0init). 29.4. performing a crc calculation once crc0 is initialized, the input data stream is sequenti ally written to crc0in, one byte at a time. the crc0 result is automatically updated after each byte is written. the crc engine may also be configured to automatically perform a crc on one or more flash se ctors. the following steps can be used to automati- cally perform a crc on flash memory. 1. prepare crc0 for a crc calculation as shown above. 2. write the index of the starting page to crc0auto. 3. set the autoen bit in crc0auto. 4. write the number of flash sectors to pe rform in the crc calculation to crc0cnt. note: each flash sector is 512 bytes. 5. write any value to crc0cn (or or its contents with 0x00) to initiate the crc calculation. the cpu will not execute code any additional code until the crc operation completes. 6. clear the autoen bit in crc0auto. 7. read the crc result using the procedure below. 29.5. accessing th e crc0 result the internal crc0 result is 32 -bits (crc0sel = 0b) or 16-bits (crc0sel = 1b). the crc0pnt bits select the byte that is targeted by read and write operations on crc0dat and increment after each read or write. the calculation re sult will remain in the internal cr0 result register until it is set, overwritten, or addi- tional data is written to crc0in. rev. 1.0 215 c8051f70x/71x sfr address = 0x91; sfr page = f sfr definition 29.1. crc0cn: crc0 control bit76543210 name crc0sel crc0init crc0val crc0pnt[1:0] type r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:5 unused read = 000b; write = don?t care. 4 crc0sel crc0 polynomial select bit. this bit selects the crc0 polynomial and result length (32-bit or 16-bit). 0: crc0 uses the 32-bit polynomial 0x 04c11db7 for calcul ating the crc result. 1: crc0 uses the 16-bit polynomial 0x1021 for calculating the crc result. 3 crc0init crc0 result init ialization bit. writing a 1 to this bit initializes th e entire crc result based on crc0val. 2 crc0val crc0 set value initialization bit. this bit selects the set value of the crc result. 0: crc result is set to 0x00000000 on write of 1 to crc0init. 1: crc result is set to 0xfff fffff on write of 1 to crc0init. 1:0 crc0pnt[1:0] crc0 result pointer. specifies the byte of the crc result to be read/written on the next access to crc0dat. the value of these bits will auto -increment upon ea ch read or write. for crc0sel = 0: 00: crc0dat accesses bits 7?0 of the 32-bit crc result. 01: crc0dat accesses bits 15?8 of the 32-bit crc result. 10: crc0dat accesses bits 23?16 of the 32-bit crc result. 11: crc0dat accesses bits 31?24 of the 32-bit crc result. for crc0sel = 1: 00: crc0dat accesses bits 7?0 of the 16-bit crc result. 01: crc0dat accesses bits 15?8 of the 16-bit crc result. 10: crc0dat accesses bits 7?0 of the 16-bit crc result. 11: crc0dat accesses bits 15?8 of the 16-bit crc result. c8051f70x/71x 216 rev. 1.0 sfr address = 0x94; sfr page = f sfr address = 0xd9; sfr page = f sfr definition 29.2. crc 0in: crc data input bit76543210 name crc0in[7:0] type r/w reset 00000000 bit name function 7:0 crc0in[7:0] crc0 data input. each write to crc0in result s in the written data being computed into the existing crc result according to the crc algorithm described in section 29.1 sfr definition 29.3. crc0data: crc data output bit76543210 name crc0dat[7:0] type r/w reset 00000000 bit name function 7:0 crc0dat[7:0] crc0 data output. each read or write performed on crc0dat targets the crc result bits pointed to by the crc0 result pointer (crc0pnt bits in crc0cn). rev. 1.0 217 c8051f70x/71x sfr address = 0x96; sfr page = f sfr address = 0x97; sfr page = f sfr definition 29.4. crc0aut o: crc automatic control bit76543210 name autoen crccpt reserved crc0st[4:0] type r/w reset 01000000 bit name function 7autoen automatic crc calc ulation enable. when autoen is set to 1, any write to crc0cn will initiate an automatic crc starting at flash sector crc0st and continuing for crc0cnt sectors. 6 crccpt automatic crc calcul ation complete. set to 0 when a crc calculation is in progress. code execution is stopped during a crc calculation, ther efore reads from firmware will always return 1. 5 reserved reserved. must write 0. 4:0 crc0st[4:0] automatic crc calculation starting flash sector. these bits specify the flash sector to start the automatic crc calculation. the starting address of the first flash sector included in the automatic crc calculation is crc0st x 512. sfr definition 29.5. crc0cnt: c rc automatic flash sector count bit76543210 name crc0cnt[5:0] type rr r/w reset 00000000 bit name function 7:6 unused read = 00b; write = don?t care. 5:0 crc0cnt[5:0] automatic crc calculation flash sector count. these bits specify the number of flash sectors to include when performing an automatic crc calculation. the base address of the last flash sector included in the automatic crc calculation is equal to (crc0st + crc0cnt) x 512. c8051f70x/71x 218 rev. 1.0 29.6. crc0 bit reverse feature crc0 includes hardware to reverse the bit order of eac h bit in a byte as shown in figure 29.1. each byte of data written to crc0flip is read back bit reversed. for example, if 0xc0 is written to crc0flip, the data read back is 0x03. bit reversal is a useful mathem atical function used in algorithms such as the fft. sfr address = 0x95; sfr page = f sfr definition 29.6. crc 0flip: crc bit flip bit76543210 name crc0flip[7:0] type r/w reset 00000000 bit name function 7:0 crc0flip[7:0] crc0 bit flip. any byte written to crc0flip is read back in a bit-reversed order, i.e. the written lsb becomes the msb. for example: if 0xc0 is written to crc0flip, the data read back will be 0x03. if 0x05 is written to crc0flip, the data read back will be 0xa0. rev. 1.0 219 c8051f70x/71x 30. smbus the smbus i/o interface is a two-wire, bi-directional serial bus. the smbus is compliant with the system management bus specification, version 1.1, and compatible with the i 2 c serial bus. reads and writes to the interface by the system contro ller are byte oriented with the smbu s interface autonomously controlling the serial transfer of the data. data can be transferre d at up to 1/20th of the system clock as a master or slave (this can be faster than allowed by the smbus specification, depending on the system clock used). a method of extending the clock-low duration is ava ilable to accommodate devices with different speed capabilities on the same bus. the smbus interface may operate as a master and/or slave, and may function on a bus with multiple mas- ters. the smbus provides control of sda (serial data), scl (serial clock) generation and synchronization, arbitration logic, and start/stop control and gene ration. the smbus peripheral can be fully driven by software (i.e., software ac cepts/rejects slave addresses, and generat es acks), or hardware slave address recognition and automatic ack generation can be enabled to minimize software overhead. a block dia- gram of the smbus peripheral and the associated sfrs is shown in figure 30.1. figure 30.1. smbus block diagram data path control smbus control logic c r o s s b a r scl filter n sda control scl control interrupt request port i/o smb0cn s t a a c k r q a r b l o s t a c k s i t x m o d e m a s t e r s t o 01 00 10 11 t0 overflow t1 overflow tmr2h overflow tmr2l overflow smb0cf e n s m b i n h b u s y e x t h o l d s m b t o e s m b f t e s m b c s 1 s m b c s 0 0 1 2 3 4 5 6 7 smb0dat sda filter n smb0adr s l v 4 s l v 2 s l v 1 s l v 0 g c s l v 5 s l v 6 s l v 3 smb0adm s l v m 4 s l v m 2 s l v m 1 s l v m 0 e h a c k s l v m 5 s l v m 6 s l v m 3 arbitration scl synchronization hardware ack generation scl generation (master mode) sda control hardware slave address recognition irq generation c8051f70x/71x 220 rev. 1.0 30.1. supporting documents it is assumed the reader is fam iliar with or has access to th e following supporting documents: 1. the i 2 c-bus and how to use it (including s pecifications), philips semiconductor. 2. the i 2 c-bus specification?version 2.0, philips semiconductor. 3. system management bus specification? version 1.1, sbs implementers forum. 30.2. smbus configuration figure 30.2 shows a typical smbus configuration. th e smbus specification allows any recessive voltage between 3.0 v and 5.0 v; different devices on the bus ma y operate at different voltage levels. the bi-direc- tional scl (serial clock) and sda (serial data) lines mu st be connected to a positive power supply voltage through a pullup resistor or similar circuit. every devi ce connected to the bus must have an open-drain or open-collector output for both the scl and sda lines, so that both are pulled high (recessive state) when the bus is free. the maximum number of devices on th e bus is limited only by th e requirement that the rise and fall times on the bus not exceed 300 ns and 1000 ns, respectively. figure 30.2. typical smbus configuration 30.3. smbus operation two types of data transfers are possible: data transfers from a master transmitter to an addressed slave receiver (write), and data transfers from an addres sed slave transmitter to a master receiver (read). the master device initiates both types of data transfer s and provides the serial clock pulses on scl. the smbus interface may operate as a master or a slave, and multiple master devices on the same bus are supported. if two or more masters attempt to initiate a data transfer simultaneously, an arbitration scheme is employed with a single master always winning the arbi tration. it is not necessary to specify one device as the master in a system; any device who transmits a start and a slave address becomes the master for the duration of that transfer. a typical smbus transaction consists of a start cond ition followed by an address byte (bits7?1: 7-bit slave address; bit0: r/w direction bit), one or more bytes of data, and a stop condition. bytes that are received (by a master or slave) are acknowledg ed (ack) with a low sda during a high scl (see figure 30.3). if the receiving device does not ack, the tran smitting device will read a nack (not acknowl- edge), which is a high sda during a high scl. the direction bit (r/w) occupies the least-significant bit position of the address byte. the direction bit is set to logic 1 to indicate a "read" operation and cleared to logic 0 to indicate a "write" operation. vdd = 5v master device slave device 1 slave device 2 vdd = 3v vdd = 5v vdd = 3v sda scl rev. 1.0 221 c8051f70x/71x all transactions are initiated by a master, with one or more addressed slave devices as the target. the master generates the start condition and then transmit s the slave address and dire ction bit. if the trans- action is a write operation from th e master to the slave, the master transmits the data a byte at a time waiting for an ack from the slave at the end of each byte. for read operations , the slave transmits the data waiting for an ack from the master at the end of each byte. at the end of the data transfer, the master generates a stop condition to term inate the transaction and free the bu s. figure 30.3 illustrates a typical smbus transaction. figure 30.3. smbus transaction 30.3.1. transmitter vs. receiver on the smbus communications interface, a device is the ?transmitter? when it is sending an address or data byte to another device on the bus. a device is a ?receiver? when an address or data byte is being sent to it from another device on the bus. the transmitter controls the sda line during the address or data byte. after each byte of address or data information is se nt by the transmitter, the receiver sends an ack or nack bit during the ack phase of the transfer, dur ing which time the receiver controls the sda line. 30.3.2. arbitration a master may start a transfer only if the bus is free. th e bus is free after a stop condition or after the scl and sda lines remain high for a specified time (see section ?30.3.5. scl high (smbus free) timeout? on page 222). in the event that two or more devices attempt to begin a transfer at the same time, an arbitra- tion scheme is employed to force one master to give up the bus. the master devices continue transmitting until one attempts a high while the other transmit s a low. since the bus is open-drain, the bus will be pulled low. the master attempting th e high will detect a low sda and lo se the arbitration. the winning master continues its transmission without interruption; the losing master becomes a slave and receives the rest of the transfer if addressed. this arbitration scheme is non-destru ctive: one device always wins, and no data is lost. 30.3.3. clock low extension smbus provides a clock synchronizati on mechanism, similar to i2c, wh ich allows devices with different speed capabilities to coexist on the bus. a clock-low extension is used du ring a transfer in order to allow slower slave devices to communica te with faster masters. the slave may temporarily hold the scl line low to extend the clock low period, effectively decreasing the serial clock frequency. 30.3.4. scl low timeout if the scl line is held low by a slave device on the bus, no further communication is possible. furthermore, the master cannot force the scl line high to correct th e error condition. to solve this problem, the smbus protocol specifies that devices participating in a tran sfer must detect any clock cycle held low longer than 25 ms as a ?timeout? condition. devices that have det ected the timeout condition must reset the communi- cation no later than 10 ms after detecting the timeout condition. when the smbtoe bit in smb0cf is set, timer 3 is used to detect scl low timeouts. timer 3 is forced to reload when scl is high, and allowed to count when scl is low. with timer 3 enabled and configured to sla6 sda sla5-0 r/w d7 d6-0 scl slave address + r/w data byte start ack nack stop c8051f70x/71x 222 rev. 1.0 overflow after 25 ms (and smbtoe set), the timer 3 interrupt service routine can be used to reset (disable and re-enable) the smbus in the event of an scl low timeout. 30.3.5. scl high (smbus free) timeout the smbus specification stipulates th at if the scl and sda lines remain high for more that 50 s, the bus is designated as free. when the sm bfte bit in smb0cf is set, the bu s will be considered free if scl and sda remain high for more than 10 smbus clock source periods (as defined by the timer configured for the smbus clock source). if the smbus is waiting to generate a master start, the start will be generated following this timeout. a clock source is required for free timeout detection, even in a slave-only implemen- tation. 30.4. using the smbus the smbus can operate in both master and slave modes. the interface provides timing and shifting con- trol for serial transfers; higher level protocol is de termined by user software. the smbus interface provides the following application-independent features: ? byte-wise serial data transfers ? clock signal generation on scl (master mode only) and sda data synchronization ? timeout/bus error recognition, as defined by the smb0cf configuration register ? start/stop timing, detection, and generation ? bus arbitration ? interrupt generation ? status information ? optional hardware recognition of slave address and automatic acknowledgement of address/data smbus interrupts are generated for each data byte or slave address that is transferred. when hardware acknowledgement is disabled, the point at which the interrupt is generated depends on whether the hard- ware is acting as a data transmitter or receiver. wh en a transmitter (i.e., sending address/data, receiving an ack), this interrupt is generated after the ack cycle so that software may read the received ack value; when receiving data (i.e., receiving address/data, send ing an ack), this interrupt is generated before the ack cycle so that software may def ine the outgoing ack value. if har dware acknowledgement is enabled, these interrupts are always generated after the ack cycle. see section 30.5 for more details on transmis- sion sequences. interrupts are also generated to indicate the beginning of a transfer when a master (start generated), or the end of a transfer when a slave (stop detected) . software should read the smb0cn (smbus control register) to find the cause of the smbus interrupt. th e smb0cn register is described in section 30.4.2; table 30.5 provides a quick smb0cn decoding reference. 30.4.1. smbus conf iguration register the smbus configuration register (s mb0cf) is used to enable the smbus master and/or slave modes, select the smbus clock source, and select the smbus timing and timeout optio ns. when the ensmb bit is set, the smbus is enabled for all master and slave events. slave events may be disabled by setting the inh bit. with slave events inhibited, the smbus in terface will still monitor the scl and sda pins; however, the interface will nack all received addresses and will not generate any slave inte rrupts. when the inh bit is set, all slave events will be inhibited following the ne xt start (interrupts will cont inue for the duration of the current transfer). rev. 1.0 223 c8051f70x/71x the smbcs1?0 bits select the smbus clock source, which is used only when operating as a master or when the free timeout detection is enabled. when operating as a master, overflows from the selected source determine the absolute minimum scl low and high times as defined in equation 30.1.the selected clock source may be shared by other peripherals so long as the timer is left running at all times. for exam- ple, timer 1 overflows may generate the smbus and ua rt baud rates simultaneously. timer configuration is covered in section ?33. timers? on page 262. equation 30.1. minimum scl high and low times the selected clock source should be configured to establish the minimum scl high and low times as per equation 30.1. when the interface is operating as a master (and scl is not driven or extended by any other devices on the bus), the typical smbus bit rate is approximated by equation 30.2. equation 30.2. typical smbus bit rate figure 30.4 shows the typical scl generation described by equation 30.2. notice that t high is typically twice as large as t low . the actual scl output may vary due to other devices on the bus (scl may be extended low by slower slave devices, or driven low by contending master devices). the bit rate when operating as a master will ne ver exceed the limits defined by equation equation 30.1. figure 30.4. typical smbus scl generation setting the exthold bit extends the minimum setup and hold times for the sda line. the minimum sda setup time defines the absolute mini mum time that sda is stable before scl transitions from low-to-high. the minimum sda hold time defines the absolute minimum time that the current sda value remains stable after scl transitions from high-to-low. exthold should be set so that the minimum setup and hold times meet the smbus specification requirements of 250 ns and 300 ns, respectively. table 30.2 shows the min- table 30.1. smbus clock source selection smbcs1 smbcs0 smbus clock source 0 0 timer 0 overflow 0 1 timer 1 overflow 1 0 timer 2 high byte overflow 1 1 timer 2 low byte overflow t highmin t lowmin 1 f clocksourceoverflow ---------------------------------- ----------- - == bitrate f clocksourceoverflow 3 --------------- ------------------------------ - = scl timer source overflows scl high timeout t low t high c8051f70x/71x 224 rev. 1.0 imum setup and hold times for the two exthold settings. setup and hold time extensions are typically necessary when sysclk is above 10 mhz. with the smbtoe bit set, timer 3 should be configured to overflow after 25 ms in order to detect scl low timeouts (see section ?3 0.3.4. scl low timeout? on page 221). th e smbus interface will force timer 3 to reload while scl is high, and allow timer 3 to count wh en scl is low. the timer 3 interrupt service routine should be used to reset smbus communication by disabling and re-enabling the smbus. smbus free timeout detection can be enabled by setting the smbfte bit. when this bit is set, the bus will be considered free if sda and scl remain high for more than 10 smbus clock source periods (see figure 30.4). table 30.2. minimum sda setup and hold times exthold minimum sda setup time minimum sda hold time 0 t low ? 4 system clocks or 1 system clock + s/w delay * 3 system clocks 1 11 system clocks 12 system clocks note: setup time for ack bit transmissions and the msb of all data transfers. when using software acknowledgement, the s/w delay occurs between the time smb0dat or ack is written and when si is cleared. note that if si is cleared in the same write that defines the outgoing ack value, s/w delay is zero. rev. 1.0 225 c8051f70x/71x sfr address = 0xc1; sfr page = 0 sfr definition 30.1. smb0cf: smbus clock/configuration bit76543210 name ensmb inh busy exthold smbtoe smbfte smbcs[1:0] type r/w r/w r r/w r/w r/w r/w reset 00000000 bit name function 7ensmb smbus enable. this bit enables the smbus interface when set to 1. when enabled, the interface constantly monitors the sda and scl pins. 6inh smbus slave inhibit. when this bit is set to logic 1, the smbu s does not generate an interrupt when slave events occur. this effectively removes the smbus slave from the bus. master mode interrupts are not affected. 5busy smbus busy indicator. this bit is set to logic 1 by hardware when a transfer is in progress. it is cleared to logic 0 when a stop or free-timeout is sensed. 4 exthold smbus setup and hold time extension enable. this bit controls the sda setup and hold times according to table 30.2. 0: sda extended setup and hold times disabled. 1: sda extended setup and hold times enabled. 3smbtoe smbus scl timeout detection enable. this bit enables scl low timeout detection. if set to logic 1, the smbus forces timer 3 to reload while scl is high and allows timer 3 to count when scl goes low. if timer 3 is configured to split mode, only the high byte of the timer is held in reload while scl is high. timer 3 should be programmed to generate interrupts at 25 ms, and the timer 3 interrupt service routine should reset smbus communication. 2smbfte smbus free timeout detection enable. when this bit is set to logic 1, the bus will be considered free if scl and sda remain high for more than 10 sm bus clock source periods. 1:0 smbcs[1:0] smbus clock source selection. these two bits select the smbus clock sour ce, which is used to generate the smbus bit rate. the selected device should be configured according to equation 30.1. 00: timer 0 overflow 01: timer 1 overflow 10: timer 2 high byte overflow 11: timer 2 low byte overflow c8051f70x/71x 226 rev. 1.0 30.4.2. smb0cn control register smb0cn is used to control the interface and to provid e status information (see sfr definition 30.2). the higher four bits of smb0cn (master, txmode, sta, and sto) form a status vector that can be used to jump to service routines. master indicates whether a device is the master or slave during the current transfer. txmode indicates whether the device is tr ansmitting or receiving data for the current byte. sta and sto indicate that a start and/or stop ha s been detected or generated since the last smbus interrupt. sta and sto are also used to generate start and stop conditions when operating as a mas- ter. writing a 1 to sta will cause the smbus interface to enter master mode and generate a start when the bus becomes free (sta is not cleared by hardwar e after the start is generated). writing a 1 to sto while in master mode will cause the interface to generate a stop and end the current transfer after the next ack cycle. if sto and sta are both set (while in master mode), a stop followed by a start will be generated. the arblost bit indicates that the interface has lost an arbitration. this may occur anytime the interface is transmitting (master or slave). a lost arbitration while operating as a slave indicates a bus error condi- tion. arblost is cleared by hardware each time si is cleared. the si bit (smbus interrupt flag) is set at the beginning and end of each transfer, after each byte frame, or when an arbitration is lost; see table 30.3 for more details. important note about the si bit: the smbus interface is stalled while si is set; thus scl is held low, and the bus is stalled until software clears si. 30.4.2.1. software ack generation when the ehack bit in register smb0 adm is cleared to 0, the firmware on the device must detect incom- ing slave addresses and ack or nack the slave addres s and incoming data bytes. as a receiver, writing the ack bit defines the outgoing ack value; as a transmitter, reading the ack bit indicates the value received during the last ack cycle. ackrq is set each ti me a byte is received, in dicating that an outgoing ack value is needed. when ackrq is set, software should write the desired outgoing value to the ack bit before clearing si. a nack will be g enerated if software does not writ e the ack bit before clearing si. sda will reflect the defined ack value immediately following a write to the ack bit; however scl will remain low until si is cleared. if a received slave address is not ackn owledged, further slave events will be ignored until the next start is detected. 30.4.2.2. hardwa re ack generation when the ehack bit in register smb0adm is set to 1, automatic slave address recognition and ack gen- eration is enabled. more detail about automatic slave address recognition can be found in section 30.4.3. as a receiver, the value currently specified by the ac k bit will be automatically sent on the bus during the ack cycle of an incoming data byte. as a transmitter, reading the ack bit indicates the value received on the last ack cycle. the ackrq bit is not used when hardware ack generation is enabled. if a received slave address is nacked by hardware, further sl ave events will be ignored until the next start is detected, and no interrupt will be generated. table 30.3 lists all sources for hardware changes to the smb0cn bits. refer to table 30.5 for smbus sta- tus decoding using the smb0cn register. rev. 1.0 227 c8051f70x/71x sfr address = 0xc0; sfr page = all pages; bit-addressable sfr definition 30.2. smb0cn: smbus control bit76543210 name master txmode sta sto ackrq arblost ack si type rrr/wr/wrrr/wr/w reset 00000000 bit name description read write 7 master smbus master/slave indicator. this read-only bit indicates when the smbus is operating as a master. 0: smbus operating in slave mode. 1: smbus operating in master mode. n/a 6txmode smbus transmit mode indicator. this read-only bit indicates when the smbus is operating as a transmitter. 0: smbus in receiver mode. 1: smbus in transmitter mode. n/a 5sta smbus start flag. 0: no start or repeated start detected. 1: start or repeated start detected. 0: no start generated. 1: when configured as a master, initiates a start or repeated start. 4sto smbus stop flag. 0: no stop condition detected. 1: stop condition detected (if in slave mode) or pend- ing (if in master mode). 0: no stop condition is transmitted. 1: when configured as a master, causes a stop condition to be transmit- ted after the next ack cycle. cleared by hardware. 3ackrq smbus acknowledge request. 0: no ack requested 1: ack requested n/a 2arblost smbus arbitration lost indicator. 0: no arbitration error. 1: arbitration lost n/a 1ack smbus acknowledge. 0: nack received. 1: ack received. 0: send nack 1: send ack 0si smbus interrupt flag. this bit is set by hardware under the conditions listed in table 15.3. si must be cleared by software. while si is set, scl is held low and the smbus is stalled. 0: no interrupt pending 1 : interrupt pending 0: clear interrupt, and initi- ate next state machine event. 1: force interrupt. c8051f70x/71x 228 rev. 1.0 30.4.3. hardware slave address recognition the smbus hardware has th e capability to automatica lly recognize incoming sl ave addresses and send an ack without software intervention. automatic slave address recognition is enabled by setting the ehack bit in register smb0adm to 1. this will enable both automatic slave address recognition and automatic hardware ack generation for received bytes (as a ma ster or slave). more detail on automatic hardware ack generation can be found in section 30.4.2.2. the registers used to define which address(es) ar e recognized by the hardware are the smbus slave address register (sfr definition 30.3) and the smbus slave address mask register (sfr definition 30.4). a single address or range of addresses (including the general call address 0x00) can be specified using these two registers. the most-significant seven bits of the two registers are used to define which addresses will be acked. a 1 in bit positions of the slave address ma sk slvm[6:0] enab le a comparison between the received slave address and the hardware?s sl ave address slv[6:0] for those bits. a 0 in a bit of the slave address mask means that bit will be treated as a ?don?t care ? for comparison purposes. in this table 30.3. sources for hardware changes to smb0cn bit set by hardware when: cleared by hardware when: master ? a start is generated. ? a stop is generated. ? arbitration is lost. txmode ? start is generated. ? smb0dat is written before the start of an smbus frame. ? a start is detected. ? arbitration is lost. ? smb0dat is not written before the start of an smbus frame. sta ? a start followed by an address byte is received. ? must be cleared by software. sto ? a stop is detected while addressed as a slave. ? arbitration is lost due to a detected stop. ? a pending stop is generated. ackrq ? a byte has been received and an ack response value is needed (only when hardware ack is not enabled). ? after each ack cycle. arblost ? a repeated start is detected as a master when sta is low (unwanted repeated start). ? scl is sensed low while attempting to generate a stop or repeated start condition. ? sda is sensed low while transmitting a 1 (excluding ack bits). ? each time si is cleared. ack ? the incoming ack value is low (acknowledge). ? the incoming ack value is high (not acknowledge). si ? a start has been generated. ? lost arbitration. ? a byte has been transmitted and an ack/nack received. ? a byte has been received. ? a start or repeated start followed by a slave address + r/w has been received. ? a stop has been received. ? must be cleared by software. rev. 1.0 229 c8051f70x/71x case, either a 1 or a 0 value are acceptable on the in coming slave address. additionally, if the gc bit in register smb0adr is set to 1, hardware will recogn ize the general call addres s (0x00). table 30.4 shows some example parameter settings and the slave addresses that will be reco gnized by hardware under those conditions. sfr address = 0xba; sfr page = f table 30.4. hardware address recognition examples (ehack = 1) hardware slave address slv[6:0] slave address mask slvm[6:0] gc bit slave addresses recognized by hardware 0x34 0x7f 0 0x34 0x34 0x7f 1 0x34, 0x00 (general call) 0x34 0x7e 0 0x34, 0x35 0x34 0x7e 1 0x34, 0x35, 0x00 (general call) 0x70 0x73 0 0x70, 0x74, 0x78, 0x7c sfr definition 30.3. smb0a dr: smbus slave address bit76543210 name slv[6:0] gc type r/w r/w reset 00000000 bit name function 7:1 slv[6:0] smbus hardware slave address. defines the smbus slave address(es) for automatic hardware acknowledgement. only address bits which have a 1 in the corresponding bit position in slvm[6:0] are checked against the incoming address. this allows multiple addresses to be recognized. 0gc general call address enable. when hardware address reco gnition is enabled (ehack = 1), this bit will deter- mine whether the general call address (0 x00) is also recognized by hardware. 0: general call ad dress is ignored. 1: general call address is recognized. c8051f70x/71x 230 rev. 1.0 sfr address = 0xbb; sfr page = f sfr definition 30.4. smb0adm : smbus slave address mask bit76543210 name slvm[6:0] ehack type r/w r/w reset 11111110 bit name function 7:1 slvm[6:0] smbus slave address mask. defines which bits of register smb0adr are compared with an incoming address byte, and which bits are ignored. any bit set to 1 in slvm[6:0] enables compari- sons with the corresponding bit in slv[6:0]. bits set to 0 are ignored (can be either 0 or 1 in the incoming address). 0ehack hardware acknowledge enable. enables hardware acknowledgement of slave address and received data bytes. 0: firmware must manually acknowledge all incoming address and data bytes. 1: automatic slave address recognition and hardware acknowledge is enabled. rev. 1.0 231 c8051f70x/71x 30.4.4. data register the smbus data register smb0dat holds a byte of serial data to be transmitted or one that has just been received. software may safely read or write to the data register when the si flag is set. software should not attempt to access the smb0dat register when the smbus is enabled and the si flag is cleared to logic 0, as the interface may be in the process of shifting a byte of data into or out of the register. data in smb0dat is always shifted ou t msb first. after a byte has been received, the first bit of received data is located at the msb of smb0dat. while data is being shifted out, data on the bus is simultaneously being shifted in. smb0dat always contains the last data byte present on the bus. in the event of lost arbi- tration, the transition from master transmitter to slave receiver is made with the correct data or address in smb0dat. sfr address = 0xc2; sfr page = 0 sfr definition 30.5. smb0dat: smbus data bit76543210 name smb0dat[7:0] type r/w reset 00000000 bit name function 7:0 smb0dat[7:0] smbus data. the smb0dat register contains a byte of data to be transmitted on the smbus serial interface or a byte that has just b een received on the smbus serial interface. the cpu can read from or write to this regi ster whenever the si serial interrupt flag (smb0cn.0) is set to logic 1. the serial data in the register remains stable as long as the si flag is set. when the si flag is not set, the system may be in the process of shifting data in/out and the cpu shou ld not attempt to access this register. c8051f70x/71x 232 rev. 1.0 30.5. smbus transfer modes the smbus interface may be configured to operate as master and/or slave. at any particular time, it will be operating in one of the following four modes: master transmitter, master receiver, slave transmitter, or slave receiver. the smbus interface enters master mo de any time a start is generated, and remains in master mode until it loses an arbitration or generates a stop. an smbus interrupt is generated at the end of all smbus byte frames. the position of the ack interrupt when operating as a receiver depends on whether hardware ack generation is enabled. as a receiver, the interrupt for an ack occurs before the ack with hardware ack generation disabled, and after the ack when hardware ack generation is enabled. as a transmitter, interrupts occur after the ack, regardless of w hether hardware ack generation is enabled or not. 30.5.1. write se quence (master) during a write sequence, an smbus ma ster writes data to a slave device . the master in th is transfer will be a transmitter during the address byte, and a transmitter during all data bytes. the smbus interface gener- ates the start condition and transmits the first byte containing the address of the target slave and the data direction bit. in this case the data direction bi t (r/w) will be logic 0 (write). the master then trans- mits one or more bytes of serial data. after each byte is transmitted, an acknowledge bit is generated by the slave. the transfer is ended wh en the sto bit is set and a stop is generated. the in terface will switch to master receiver mode if smb0 dat is not written following a master transmitter interrupt. figure 30.5 shows a typical master write sequence. two transmit data bytes are shown, though any number of bytes may be transmitted. notice that all of the ?data byte transferred? interrupts occur after the ack cycle in this mode, regardless of whether hard ware ack generation is enabled. figure 30.5. typical master write sequence a a a s w p data byte data byte sla s = start p = stop a = ack w = write sla = slave address received by smbus interface transmitted by smbus interface interrupts with hardware ack disabled (ehack = 0) interrupts with hardware ack enabled (ehack = 1) rev. 1.0 233 c8051f70x/71x 30.5.2. read sequence (master) during a read sequence, an smbus ma ster reads data from a slave devic e. the master in this transfer will be a transmitter during the address byte, and a receiv er during all data bytes. the smbus interface gener- ates the start condition and transmits the first byte containing the address of the target slave and the data direction bit. in this case the data directi on bit (r/w) will be logic 1 (read). serial data is then received from the slave on sda while the smbus outputs the serial clock. the slave transmits one or more bytes of serial data. if hardware ack generation is disabled, the ackrq is set to 1 and an interrupt is generated after each received byte. software must writ e the ack bit at that time to ack or nack the received byte. with hardware ack generation enab led, the smbus hardware will automatically generate the ack/nack, and then post the interrupt. it is important to note that the appropriate ack or nack value should be set up by the software prior to receiving the byte when hardware ack generation is enabled. writing a 1 to the ack bit generates an ack; writing a 0 generates a nack. software should write a 0 to the ack bit for the last data transfer, to transmit a nack. the interface exits master receiver mode after the sto bit is set and a stop is generated. the in terface will switch to master transmitter mode if smb0dat is written while an active master receiver. figure 30.6 shows a typical master read sequence. two received data bytes are shown, though any number of bytes may be received. notice that the ?data byte transferred? interrupts occur at different places in the sequence, depending on whether hardware ack generation is enabled. the interrupt occurs before the ack with hardware ack generation disabled, and after the ack when hardware ack generation is enabled. figure 30.6. typical master read sequence data byte data byte a n a s r p sla s = start p = stop a = ack n = nack r = read sla = slave address received by smbus interface transmitted by smbus interface interrupts with hardware ack disabled (ehack = 0) interrupts with hardware ack enabled (ehack = 1) c8051f70x/71x 234 rev. 1.0 30.5.3. write sequence (slave) during a write sequence, an smbus ma ster writes data to a slave device. the slave in this transfer will be a receiver during the address byte, and a receiver during all data bytes. when slave events are enabled (inh = 0), the interface enters slave receiver mode when a start followed by a slave address and direc- tion bit (write in this case) is received. if hardware ack generation is disabled, upon entering slave receiver mode, an interrupt is generated and the ac krq bit is set. the software must respond to the received slave address with an ack, or ignore the received slave address with a nack. if hardware ack generation is enabled, the hardware will apply the ac k for a slave address which matches the criteria set up by smb0adr and smb0adm. the inte rrupt will occur after the ack cycle. if the received slave address is ignore d (by software or hardware), slav e interrupts will be in hibited until the next start is detected. if the received slave address is acknowledged, zero or more data bytes are received. if hardware ack generation is disabled, the ackrq is set to 1 and an interrupt is generated after each received byte. software must writ e the ack bit at that time to ack or nack the received byte. with hardware ack generation enab led, the smbus hardware will automatically generate the ack/nack, and then post the interrupt. it is important to note that the appropriate ack or nack value should be set up by the software prior to receiving the byte when hardware ack generation is enabled. the interface exits slave receiver mode after receiving a stop. the in terface will switch to slave trans- mitter mode if smb0dat is written wh ile an active slave receiver. figu re 30.7 shows a typical slave write sequence. two received data bytes are shown, thou gh any number of bytes may be received. notice that the ?data byte transferred? interrupts occur at differ ent places in the sequence, depending on whether hard- ware ack generation is enabled. the interrupt occurs before the ack with hardware ack generation dis- abled, and after the ack when hardware ack generation is enabled. figure 30.7. typical slave write sequence p w sla s data byte data byte a a a s = start p = stop a = ack w = write sla = slave address received by smbus interface transmitted by smbus interface interrupts with hardware ack disabled (ehack = 0) interrupts with hardware ack enabled (ehack = 1) rev. 1.0 235 c8051f70x/71x 30.5.4. read se quence (slave) during a read sequence, an smbus ma ster reads data from a slave device. the slave in this transfer will be a receiver during the address byte, and a transm itter during all data bytes. when slave events are enabled (inh = 0), the interface enters slave receiver mode (to receive the slave address) when a start followed by a slave address and direction bit (read in this case) is received. if hardware ack generation is disabled, upon entering slave receiver mode, an interrupt is generated and the ackrq bit is set. the software must respond to the received slave address with an ack, or ignore the received slave address with a nack. if hardware ack generat ion is enabled, the hardware will apply the ack for a slave address which matches the criteria set up by smb0adr and smb0adm. the interrupt will occur after the ack cycle. if the received slave address is ignore d (by software or hardware), slav e interrupts will be in hibited until the next start is detected. if the received slave address is acknowledged, zero or more data bytes are trans- mitted. if the received slave address is acknowledged, data should be written to smb0dat to be transmit- ted. the interface enters slave transmitter mode, and transmits one or more bytes of data. after each byte is transmitted, the master sends an acknowledge bit; if the acknowledge bit is an ack, smb0dat should be written with the next data byte. if the acknowle dge bit is a nack, smb0dat should not be written to before si is cleared (an error condition may be generated if smb0dat is written followin g a received nack while in slave transmitter mode ). the interface exits slave transmitter mode after receiving a stop. the interface will switch to slave receiver mode if smb0dat is not written following a slave transmitter interrupt. figure 30.8 shows a typical slave read sequence. two transmitted data bytes are shown, though any number of bytes may be transmitted. notice that all of the ?data byte transferred? interrupts occur after the ack cycle in this mode, regardless of whether hardware ack generation is enabled. figure 30.8. typical slave read sequence 30.6. smbus status decoding the current smbus status can be easily decoded usin g the smb0cn register. the appropriate actions to take in response to an smbus event depend on whether hardware slave address recognition and ack generation is enabled or disabled. table 30.5 describes the typical actions when hardware slave address recognition and ack generation is disabled. table 30.6 describes the typical actions when hardware slave address recognition and ack generation is enabled. in the tables, status vector refers to the four upper bits of smb0cn: master, tx mode, sta, and sto. the shown response options are only the typ- ical responses; application-specific procedures are allo wed as long as they conform to the smbus specifi- cation. highlighted responses are allowed by hardwar e but do not conform to the smbus specification. p r sla s data byte data byte a n a s = start p = stop n = nack r = read sla = slave address received by smbus interface transmitted by smbus interface interrupts with hardware ack disabled (ehack = 0) interrupts with hardware ack enabled (ehack = 1) c8051f70x/71x 236 rev. 1.0 table 30.5. smbus status decoding: hardware ack disabled (ehack = 0) mode values read current smbus state typical response options values to write next status vector expected status vector ackrq arblost ack sta sto ack master transmitter 1110 0 0 x a master start was gener- ated. load slave address + r/w into smb0dat. 00x1100 1100 000 a master data or address byte was transmitted; nack received. set sta to restart transfer. 1 0 x 1110 abort transfer. 01x ? 001 a master data or address byte was transmitted; ack received. load next data byte into smb0dat. 00x1100 end transfer with stop. 0 1 x ? end transfer with stop and start another transfer. 11x ? send repeated start. 1 0 x 1110 switch to master receiver mode (clear si without writing new data to smb0dat). 0 0 x 1000 master receiver 1000 1 0 x a master data byte was received; ack requested. acknowledge received byte; read smb0dat. 0 0 1 1000 send nack to indi cate last byte, and send stop. 010 ? send nack to indi cate last byte, and send stop followed by start. 1101110 send ack followed by repeated start. 1011110 send nack to indi cate last byte, and send repeated start. 1001110 send ack and switch to master transmitter mode (write to smb0dat before clearing si). 0 0 1 1100 send nack and switch to mas- ter transmitter mode (write to smb0dat before clearing si). 0 0 0 1100 rev. 1.0 237 c8051f70x/71x slave transmitter 0100 000 a slave byte was transmitted; nack received. no action required (expecting stop condition). 0 0 x 0001 001 a slave byte was transmitted; ack received. load smb0dat with next data byte to transmit. 0 0 x 0100 01x a slave byte was transmitted; error detected. no action required (expecting master to end transfer). 0 0 x 0001 0101 0 x x an illegal stop or bus error was detected while a slave transmission was in progress. clear sto. 00x ? slave receiver 0010 10x a slave address + r/w was received; ack requested. if write, ackno wledge received address 0 0 1 0000 if read, load smb0dat with data byte; ack received address 0 0 1 0100 nack received address. 0 0 0 ? 11x lost arbitration as master; slave address + r/w received; ack requested. if write, ackno wledge received address 0 0 1 0000 if read, load smb0dat with data byte; ack received address 0 0 1 0100 nack received address. 0 0 0 ? reschedule failed transfer; nack received address. 1001110 0001 00x a stop was detected while addressed as a slave trans- mitter or slave receiver. clear sto. 00x ? 11x lost arbitration while attempt- ing a stop. no action required (transfer complete/aborted). 000 ? 0000 1 0 x a slave byte was received; ack requested. acknowledge received byte; read smb0dat. 0 0 1 0000 nack received byte. 0 0 0 ? table 30.5. smbus status decoding: hardware ack disabled (ehack = 0) (continued) mode values read current smbus state typical response options values to write next status vector expected status vector ackrq arblost ack sta sto ack c8051f70x/71x 238 rev. 1.0 bus error condition 0010 0 1 x lost arbitration while attempt- ing a repeated start. abort failed transfer. 0 0 x ? reschedule failed transfer. 1 0 x 1110 0001 0 1 x lost arbitration due to a detected stop. abort failed transfer. 0 0 x ? reschedule failed transfer. 1 0 x 1110 0000 1 1 x lost arbitration while transmit- ting a data byte as master. abort failed transfer. 0 0 0 ? reschedule failed transfer. 1 0 0 1110 table 30.6. smbus status decoding: hardware ack enabled (ehack = 1) mode values read current smbus state typical response options values to write next status vector expected status vector ackrq arblost ack sta sto ack master transmitter 1110 0 0 x a master start was gener- ated. load slave address + r/w into smb0dat. 00x1100 1100 000 a master data or address byte was transmitted; nack received. set sta to restart transfer. 1 0 x 1110 abort transfer. 01x ? 001 a master data or address byte was transmitted; ack received. load next data byte into smb0dat. 00x1100 end transfer with stop. 0 1 x ? end transfer with stop and start another transfer. 11x ? send repeated start. 1 0 x 1110 switch to master receiver mode (clear si without writing new data to smb0dat). set ack for initial data byte. 0 0 1 1000 table 30.5. smbus status decoding: hardware ack disabled (ehack = 0) (continued) mode values read current smbus state typical response options values to write next status vector expected status vector ackrq arblost ack sta sto ack rev. 1.0 239 c8051f70x/71x master receiver 1000 001 a master data byte was received; ack sent. set ack for next data byte; read smb0dat. 0 0 1 1000 set nack to indicate next data byte as the last data byte; read smb0dat. 0 0 0 1000 initiate repeated start. 1 0 0 1110 switch to master transmitter mode (write to smb0dat before clearing si). 0 0 x 1100 000 a master data byte was received; nack sent (last byte). read smb0dat; send stop. 0 1 0 ? read smb0dat; send stop followed by start. 1101110 initiate repeated start. 1 0 0 1110 switch to master transmitter mode (write to smb0dat before clearing si). 0 0 x 1100 slave transmitter 0100 000 a slave byte was transmitted; nack received. no action required (expecting stop condition). 0 0 x 0001 001 a slave byte was transmitted; ack received. load smb0dat with next data byte to transmit. 0 0 x 0100 01x a slave byte was transmitted; error detected. no action required (expecting master to end transfer). 0 0 x 0001 0101 0 x x an illegal stop or bus error was detected while a slave transmission was in progress. clear sto. 00x ? table 30.6. smbus status decoding: hardware ack enabled (ehack = 1) (continued) mode values read current smbus state typical response options values to write next status vector expected status vector ackrq arblost ack sta sto ack c8051f70x/71x 240 rev. 1.0 slave receiver 0010 00x a slave address + r/w was received; ack sent. if write, set ack for first data byte. 0 0 1 0000 if read, load smb0dat with data byte 0 0 x 0100 01x lost arbitration as master; slave address + r/w received; ack sent. if write, set ack for first data byte. 0 0 1 0000 if read, load smb0dat with data byte 0 0 x 0100 reschedule failed transfer 1 0 x 1110 0001 00x a stop was detected while addressed as a slave trans- mitter or slave receiver. clear sto. 00x ? 01x lost arbitration while attempt- ing a stop. no action required (transfer complete/aborted). 000 ? 0000 0 0 x a slave byte was received. set ack for next data byte; read smb0dat. 0 0 1 0000 set nack for next data byte; read smb0dat. 0 0 0 0000 bus error condition 0010 0 1 x lost arbitration while attempt- ing a repeated start. abort failed transfer. 0 0 x ? reschedule failed transfer. 1 0 x 1110 0001 0 1 x lost arbitration due to a detected stop. abort failed transfer. 0 0 x ? reschedule failed transfer. 1 0 x 1110 0000 0 1 x lost arbitration while transmit- ting a data byte as master. abort failed transfer. 0 0 x ? reschedule failed transfer. 10x1110 table 30.6. smbus status decoding: hardware ack enabled (ehack = 1) (continued) mode values read current smbus state typical response options values to write next status vector expected status vector ackrq arblost ack sta sto ack rev. 1.0 241 c8051f70x/71x 31. enhanced serial pe ripheral interface (spi0) the enhanced serial peripheral interface (spi0) pr ovides access to a flexible, full-duplex synchronous serial bus. spi0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports mul- tiple masters and slaves on a single spi bus. the slave-select (nss) signal can be configured as an input to select spi0 in slave mode, or to disable master mode operation in a multi-master environment, avoiding contention on the spi bus when more than one master attempts simultaneous data transfers. nss can also be configured as a chip-select output in master mode, or disabled for 3-wire operation. additional gen- eral purpose port i/o pins can be used to se lect multiple slave dev ices in master mode. figure 31.1. spi block diagram sfr bus data path control sfr bus write spi0dat receive data buffer spi0dat 0 1 2 3 4 5 6 7 shift register spi control logic spi0ckr scr7 scr6 scr5 scr4 scr3 scr2 scr1 scr0 spi0cfg spi0cn pin interface control pin control logic c r o s s b a r port i/o read spi0dat spi irq tx data rx data sck mosi miso nss transmit data buffer clock divide logic sysclk ckpha ckpol slvsel nssmd1 nssmd0 spibsy msten nssin srmt rxbmt spif wcol modf rxovrn txbmt spien c8051f70x/71x 242 rev. 1.0 31.1. signal descriptions the four signals used by spi0 (mosi, miso, sck, nss) are described below. 31.1.1. master out, slave in (mosi) the master-out, slave-in (mosi) signal is an output fr om a master device and an input to slave devices. it is used to serially transfer data from the master to th e slave. this signal is an output when spi0 is operat- ing as a master and an input when spi0 is operating as a slave. data is transferred most-significant bit first. when configured as a master, mosi is driven by the msb of the shift register in both 3- and 4-wire mode. 31.1.2. master in, slave out (miso) the master-in, slave-out (miso) signal is an output fr om a slave device and an input to the master device. it is used to serially transfer data from the slave to the master. this signal is an input when spi0 is operat- ing as a master and an output when spi0 is operating as a slave. data is transferred most-significant bit first. the miso pin is placed in a high-impedance st ate when the spi module is disabled and when the spi operates in 4-wire mode as a slave that is not select ed. when acting as a slave in 3-wire mode, miso is always driven by the msb of the shift register. 31.1.3. serial clock (sck) the serial clock (sck) signal is an output from the ma ster device and an input to slave devices. it is used to synchronize the transfer of data between the mast er and slave on the mosi and miso lines. spi0 gen- erates this signal when operating as a master. the sck signal is ignored by a spi slave when the slave is not selected (nss = 1) in 4-wire slave mode. 31.1.4. slave select (nss) the function of the slave-select (nss) signal is dependent on the setting of the nssmd1 and nssmd0 bits in the spi0cn register. there are three possib le modes that can be selected with these bits: 1. nssmd[1:0] = 00: 3-wire master or 3-wire slave mode: spi0 operates in 3-wire mode, and nss is disabled. when operating as a slave device, spi0 is always selected in 3-wire mode. since no select signal is present, spi0 must be the only slave on the bus in 3-wire mode. this is intended for point-to- point communication between a master and one slave. 2. nssmd[1:0] = 01: 4-wire slave or multi-master mode: spi0 operates in 4-wire mode, and nss is enabled as an input. when operating as a slave, nss selects the spi0 device. when operating as a master, a 1-to-0 transition of the nss signal disabl es the master function of spi0 so that multiple master devices can be used on the same spi bus. 3. nssmd[1:0] = 1x: 4-wire master mode: spi0 oper ates in 4-wire mode, and nss is enabled as an output. the setting of nssmd0 dete rmines what logic level the nss pin will output. this configuration should only be used when operating spi0 as a master device. see figure 31.2, figure 31.3, and figure 31.4 for typica l connection diagrams of the various operational modes. note that the setting of nssmd bits affects the pinout of the device. when in 3-wire master or 3-wire slave mode, the nss pin will not be mapped by the crossbar. in all other modes, the nss signal will be mapped to a pin on the device. see section ?28. port input/output? on page 180 for general purpose port i/o and crossbar information. 31.2. spi0 master mode operation a spi master device initiates all data transfers on a spi bus. spi0 is placed in master mode by setting the master enable flag (msten, spi0cn.6). writing a byte of data to the spi0 data register (spi0dat) when in master mode writes to the transmit buffer. if the spi shift register is empty, the byte in the transmit buffer is moved to the shift register, and a data transfer begins. the spi0 master immediately shifts out the data serially on the mosi line while provid ing the serial clock on sck. the spi f (spi0cn.7) flag is set to logic rev. 1.0 243 c8051f70x/71x 1 at the end of the transfer. if interrupts are enabl ed, an interrupt request is generated when the spif flag is set. while the spi0 master transf ers data to a slave on the mosi line, the addressed spi slave device simultaneously transfers the contents of its shift register to the spi master on the miso line in a full-duplex operation. therefore, the spif flag serves as both a transmit-complete and receive-data-ready flag. the data byte received from the slave is transferred msb- first into the master's shift register. when a byte is fully shifted into the register, it is moved to the re ceive buffer where it can be read by the processor by reading spi0dat. when configured as a master, spi0 can operate in one of three different modes: multi-master mode, 3-wire single-master mode, and 4-wire single-master mode. the default, multi-master mode is active when nssmd1 (spi0cn.3) = 0 and nssmd0 (spi0cn.2) = 1. in this mode, nss is an input to the device, and is used to disable the master spi0 when another ma ster is accessing the bus. when nss is pulled low in this mode, msten (spi0cn.6) and spien (spi0cn.0) ar e set to 0 to disable the spi master device, and a mode fault is generate d (modf, spi0cn.5 = 1). mode fault will gen erate an inte rrupt if enabled. spi0 must be manually re-enabled in soft ware under these circumstances. in multi-master systems, devices will typically default to being slave devices while they are not acting as the system master device. in multi-mas- ter mode, slave devices can be addressed individua lly (if needed) using general-purpose i/o pins. figure 31.2 shows a connection diagram between two master devices in multiple-mas ter mode. 3-wire single-master mode is active when nssmd1 (s pi0cn.3) = 0 and nssmd0 (spi0cn.2) = 0. in this mode, nss is not used, and is not mapped to an exte rnal port pin through the crossbar. any slave devices that must be addressed in this mode should be selected using general-purpose i/o pins. figure 31.3 shows a connection diagram between a master dev ice in 3-wire master mode and a slave device. 4-wire single-master mode is active wh en nssmd1 (spi0cn.3) = 1. in th is mode, nss is configured as an output pin, and can be used as a slave-select signal for a single spi dev ice. in this mode, the output value of nss is controlled (in software) with the bit n ssmd0 (spi0cn.2). additional slave devices can be addressed using general-purpose i/o pins. figure 31.4 shows a connection diagram for a master device in 4-wire master mode and two slave devices. figure 31.2. multiple-master mode connection diagram figure 31.3. 3-wire single master and single slave mode connection diagram master device 2 master device 1 mosi miso sck miso mosi sck nss gpio nss gpio slave device master device mosi miso sck miso mosi sck c8051f70x/71x 244 rev. 1.0 figure 31.4. 4-wire single master mode and slave mode connection diagram 31.3. spi0 slave mode operation when spi0 is enabled and not confi gured as a master, it will operate as a spi slave. as a slave, bytes are shifted in through the mosi pin a nd out through the miso pin by a ma ster device controlling the sck sig- nal. a bit counter in the spi0 logic counts sck edges . when 8 bits have been shifted through the shift reg- ister, the spif flag is set to logic 1, and the byte is copied into the receive buffer. data is read from the receive buffer by reading spi0dat. a slave device cannot initiate transfers. data to be transferred to the master device is pre-loaded into the shift register by writing to spi0dat. writes to spi0dat are double- buffered, and are placed in the transmit buffer first. if the shift register is empty, the contents of the transmit buffer will immediately be transferred into the shift register. when the sh ift register already contains data, the spi will load the shift register wi th the transmit buffer?s contents af ter the last sck edge of the next (or current) spi transfer. when configured as a slave, spi0 can be configured for 4-wire or 3-wire operation. the default, 4-wire slave mode, is active when nssmd1 (spi0cn.3) = 0 and nssmd0 (spi0cn.2) = 1. in 4-wire mode, the nss signal is routed to a port pin and configured as a digital input. spi0 is enabled when nss is logic 0, and disabled when nss is logic 1. the bit counter is reset on a fa lling edge of nss. the nss signal must be driven low at least 2 system clocks before th e first active edge of sck for each byte transfer. figure 31.4 shows a connection diagram between tw o slave devices in 4-wire slave mode and a master device. 3-wire slave mode is active when nssmd1 (spi0cn. 3) = 0 and nssmd0 (spi0cn.2) = 0. nss is not used in this mode, and is not mapped to an external port pin through the crossbar. since there is no way of uniquely addressing the device in 3-wire slave mode , spi0 must be the only slav e device present on the bus. it is important to note that in 3-wire slave mode there is no external means of resetting the bit counter that determines when a full byte has been received. th e bit counter can only be reset by disabling and re- enabling spi0 with the spien bit. figure 31.3 shows a connection diagram between a slave device in 3- wire slave mode and a master device. slave device master device mosi miso sck miso mosi sck nss nss gpio slave device mosi miso sck nss rev. 1.0 245 c8051f70x/71x 31.4. spi0 interrupt sources when spi0 interrupts are e nabled, the following four flags will gener ate an interrupt when they are set to logic 1: all of the following bits must be cleared by software. ? the spi interrupt flag, spif (spi0cn.7) is set to logic 1 at the end of each byte transfer. this flag can occur in all spi0 modes. ? the write collision flag, wcol (spi0cn.6) is set to logic 1 if a write to spi0dat is attempted when the transmit buffer has not been emptied to the spi shift register. when this occurs, the write to spi0dat will be ignored, and the tr ansmit buffer will not be written.this flag can occur in all spi0 modes. ? the mode fault flag modf (spi0cn.5) is set to logi c 1 when spi0 is configured as a master, and for multi-master mode and the nss pin is pulled low. when a mode fault occurs, the msten and spien bits in spi0cn are set to logic 0 to disable spi0 and allow another master device to access the bus. ? the receive overrun flag rxovrn (spi0cn.4) is se t to logic 1 when configured as a slave, and a transfer is completed and the rece ive buffer still holds an unread byte from a prev ious transfer. the new byte is not transferred to the receive buffer, allowing the previously received data byte to be read. the data byte which caused the overrun is lost. 31.5. serial clock phase and polarity four combinations of serial clock phase and polarity can be selected using the clock control bits in the spi0 configuration register (spi0cfg). the ckpha bit ( spi0cfg.5) selects one of two clock phases (edge used to latch the data). the ckpol bit (spi0cfg.4) selects between an active-high or active-low clock. both master and slave devices must be config ured to use the same clock phase and polarity. spi0 should be disabled (by clearing the spien bit, spi0cn.0) when changing the clock phase or polarity. the clock and data line relationships for master mode are shown in figure 31.5. for slave mode, the clock and data relationships are shown in figure 31.6 and figure 3 1.7. ckpha should be set to 0 on both the master and slave spi when communicating betw een two silicon labs c8051 devices. the spi0 clock rate register (spi 0ckr) as shown in sfr definition 31.3 controls the master mode serial clock frequency. this register is ignored wh en operating in slave mode. when the spi is configured as a master, the maximum data transfer rate (bits/sec) is one-half the system clock frequency or 12.5 mhz, whichever is slower. when the spi is configured as a sl ave, the maximum data transfer rate (bits/sec) for full-duplex operation is 1/10 the system clock frequency , provided that the master issues sck, nss (in 4- wire slave mode), and the serial input data synchrono usly with the slave?s system clock. if the master issues sck, nss, and t he serial input data asynchronously, the maximum data transfer rate (bits/sec) must be less than 1/10 the system clock frequency. in the special case where the master only wants to transmit data to the slave and does not need to receive data from the slave (i.e., half-duplex operation), the spi slave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency. this is provided that the master i ssues sck, nss, and the serial inpu t data synchronously with the slave?s system clock. c8051f70x/71x 246 rev. 1.0 figure 31.5. master mode data/clock timing figure 31.6. slave mode data/clock timing (ckpha = 0) sck (ckpol=0, ckpha=0) sck (ckpol=0, ckpha=1) sck (ckpol=1, ckpha=0) sck (ckpol=1, ckpha=1) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 miso/mosi nss (must remain high in multi-master mode) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 miso nss (4-wire mode) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mosi sck (ckpol=0, ckpha=0) sck (ckpol=1, ckpha=0) rev. 1.0 247 c8051f70x/71x figure 31.7. slave mode data/clock timing (ckpha = 1) 31.6. spi special function registers spi0 is accessed and controlled through four special function registers in the system controller: spi0cn control register, spi0dat data register, spi0cf g configuration register, and spi0ckr clock rate register. the four special function registers related to the operation of the spi0 bus are described in the following figures. sck (ckpol=0, ckpha=1) sck (ckpol=1, ckpha=1) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 miso nss (4-wire mode) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mosi c8051f70x/71x 248 rev. 1.0 sfr address = 0xa1; sfr page = 0 sfr definition 31.1. spi0c fg: spi0 configuration bit7654321 0 name spibsy msten ckpha ckpol slvsel nssin srmt rxbmt type r r/w r/w r/w r r r r reset 0000011 1 bit name function 7 spibsy spi busy. this bit is set to logic 1 when a spi transf er is in progress (master or slave mode). 6 msten master mode enable. 0: disable master mode. operate in slave mode. 1: enable master mode. operate as a master. 5 ckpha spi0 clock phase. 0: data centered on first edge of sck period. * 1: data centered on second edge of sck period. * 4ckpol spi0 clock polarity. 0: sck line low in idle state. 1: sck line high in idle state. 3 slvsel slave selected flag. this bit is set to logic 1 whenever the nss pin is low indicating spi0 is the selected slave. it is cleared to logic 0 when nss is high (slave not sele cted). this bit does not indicate the instantaneous value at th e nss pin, but rather a de-glitched ver- sion of the pin input. 2 nssin nss instantaneous pin input. this bit mimics the instantaneous value that is present on the nss port pin at the time that the register is read. this input is not de-glitched. 1srmt shift register empty (valid in slave mode only). this bit will be set to logic 1 when all data has been tran sferred in/out of the shift register, and there is no new information avai lable to read from the transmit buffer or write to the receive buffer . it returns to logic 0 when a data byte is transferred to the shift register from the transmit buffer or by a transition on sck. srmt = 1 when in master mode. 0 rxbmt receive buffer empty (valid in slave mode only). this bit will be set to logic 1 when the re ceive buffer has been read and contains no new information. if there is new informatio n available in the receive buffer that has not been read, this bit will return to logic 0. rxbmt = 1 when in master mode. note: in slave mode, data on mosi is sampl ed in the center of each data bit. in master mode, data on miso is sampled one sysclk before the end of each data bit, to provide maximum settling time for the slave device. see table 31.1 for timing parameters. rev. 1.0 249 c8051f70x/71x sfr address = 0xf8; sfr page = all pages; bit-addressable sfr definition 31.2. spi0cn: spi0 control bit7654321 0 name spif wcol modf rxovrn nssmd[1:0] txbmt spien type r/w r/w r/w r/w r/w r r/w reset 0000011 0 bit name function 7 spif spi0 interrupt flag. this bit is set to logic 1 by hardware at the end of a data transfer. if spi interrupts are enabled, an inte rrupt will be gene rated. this bit is not automatically cleared by hardware, and must be cleared by software. 6wcol write collision flag. this bit is set to logic 1 if a write to spi0dat is attempted when txbmt is 0. when this occurs, the write to spi0dat will be i gnored, and th e transmit buffer will not be written. if spi interrupts are enabled, an in terrupt will be generated. this bit is not automatically cleared by hardware, and must be cleared by software. 5modf mode fault flag. this bit is set to logic 1 by hardware w hen a master mode co llision is detected (nss is low, msten = 1, and nssmd[1:0] = 01). if spi interrupts are enabled, an interrupt will be generat ed. this bit is not automatica lly cleared by hardware, and must be cleared by software. 4 rxovrn receive overrun flag (valid in slave mode only). this bit is set to logic 1 by hardware w hen the receive buffer still holds unread data from a previous transfer and the last bit of the current transfer is shifted into the spi0 shift register. if spi inte rrupts are enabled, an interrupt will be generated. this bit is not automatically cleared by hardware, and must be cleared by software. 3:2 nssmd[1:0] slave select mode. selects between the following nss operation modes: (see section 31.2 and section 31.3). 00: 3-wire slave or 3-wire master mode. nss signal is not routed to a port pin. 01: 4-wire slave or multi-master mode (d efault). nss is an input to the device. 1x: 4-wire single-master mode. nss sign al is mapped as an output from the device and will assume the value of nssmd0. 1 txbmt transmit buffer empty. this bit will be set to logic 0 when new da ta has been written to the transmit buffer. when data in the transmit buff er is transferred to the spi shift register, this bit will be set to logic 1, indicating that it is safe to write a new byte to the transmit buffer. 0 spien spi0 enable. 0: spi disabled. 1: spi enabled. c8051f70x/71x 250 rev. 1.0 sfr address = 0xa2; sfr page = f sfr address = 0xa3; sfr page = 0 sfr definition 31.3. spi0ckr: spi0 clock rate bit7654321 0 name scr[7:0] type r/w reset 0000000 0 bit name function 7:0 scr[7:0] spi0 clock rate. these bits determine the frequency of the sck output when the spi0 module is configured for master mode operation. the sck clock frequency is a divided ver- sion of the system clock, and is given in the following equation, where sysclk is the system clock frequency and spi0ckr is the 8-bit value held in the spi0ckr register. for 0 <= spi0ckr <= 255 example: if sysclk = 2 m hz and spi0ckr = 0x04, sfr definition 31.4. spi0dat: spi0 data bit7654321 0 name spi0dat[7:0] type r/w reset 0000000 0 bit name function 7:0 spi0dat[7:0] spi0 transmit and receive data. the spi0dat register is used to transmit and receive spi0 data. writing data to spi0dat places the data into the transmi t buffer and initiates a transfer when in master mode. a read of spi0dat returns the contents of the receive buffer. f sck sysclk 2 spi0ckr[7:0] 1 + ?? ? ------------------- --------------------------------------- - = f sck 2000000 241 + ?? ? -------------------------- = f sck 200 khz = rev. 1.0 251 c8051f70x/71x figure 31.8. spi master timing (ckpha = 0) figure 31.9. spi master timing (ckpha = 1) sck* t mckh t mckl mosi t mis miso * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t mih sck* t mckh t mckl miso t mih mosi * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t mis c8051f70x/71x 252 rev. 1.0 figure 31.10. spi slave timing (ckpha = 0) figure 31.11. spi slave timing (ckpha = 1) sck* t se nss t ckh t ckl mosi t sis t sih miso t sd t soh * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t sez t sdz sck* t se nss t ckh t ckl mosi t sis t sih miso t sd t soh * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t slh t sez t sdz rev. 1.0 253 c8051f70x/71x table 31.1. spi slave timing parameters parameter description min max units master mode timing (see figure 31.8 and figure 31.9) t mckh sck high time 1 x t sysclk ?ns t mckl sck low time 1 x t sysclk ?ns t mis miso valid to sck shift edge 1 x t sysclk + 20 ? ns t mih sck shift edge to miso change 0 ? ns slave mode timing (see figure 31.10 and figure 31.11) t se nss falling to first sck edge 2 x t sysclk ?ns t sd last sck edge to nss rising 2 x t sysclk ?ns t sez nss falling to miso valid ? 4 x t sysclk ns t sdz nss rising to miso high-z ? 4 x t sysclk ns t ckh sck high time 5 x t sysclk ?ns t ckl sck low time 5 x t sysclk ?ns t sis mosi valid to sck sample edge 2 x t sysclk ?ns t sih sck sample edge to mosi change 2 x t sysclk ?ns t soh sck shift edge to miso change ? 4 x t sysclk ns t slh last sck edge to miso change (ckpha = 1 only) 6xt sysclk 8xt sysclk ns note: t sysclk is equal to one per iod of the device syst em clock (sysclk). c8051f70x/71x 254 rev. 1.0 32. uart0 uart0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 uart. enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details in section ?32.1. enhanced baud rate generation? on page 255). received data buffering allows uart0 to start reception of a second incoming data byte be fore software has finished reading the previous data byte. uart0 has two associated sfrs: serial control regist er 0 (scon0) and serial data buffer 0 (sbuf0). the single sbuf0 location provides access to both transmit and receive registers. writes to sbuf0 always access the transmit register. reads of sbuf0 always access the buffered receive register; it is not possible to read data from the transmit register. with uart0 interrupts enabled, an interrupt is generated each time a transmit is completed (ti0 is set in scon0), or a data byte has been received (ri0 is set in scon0). the uart0 interrupt flags are not cleared by hardware when the cpu vectors to the inte rrupt service routine. they must be cleared manually by software, allowing software to determine the cause of the uart0 interrupt (transmit complete or receive complete). figure 32.1. uart0 block diagram uart baud rate generator ri scon ri ti rb8 tb8 ren mce smode tx control tx clock send sbuf (tx shift) start data write to sbuf crossbar tx shift zero detector tx irq set qd clr stop bit tb8 sfr bus serial port interrupt ti port i/o rx control start rx clock load sbuf shift 0x1ff rb8 rx irq input shift register (9 bits) load sbuf read sbuf sfr bus crossbar rx sbuf (rx latch) rev. 1.0 255 c8051f70x/71x 32.1. enhanced ba ud rate generation the uart0 baud rate is generated by timer 1 in 8-bit auto-reload mode. the tx clock is generated by tl1; the rx clock is generated by a copy of tl1 (shown as rx timer in figure 32.2), which is not user- accessible. both tx and rx timer overflows are divided by two to generate the tx and rx baud rates. the rx timer runs when timer 1 is enabled, and uses the same reload value (th1). however, an rx timer reload is forced when a start condition is detected on the rx pin. this allows a receive to begin any time a start is detected, independent of the tx timer state. figure 32.2. uart0 baud rate logic timer 1 should be configured for mode 2, 8-bit aut o-reload (see section ?33.1.3. mode 2: 8-bit coun- ter/timer with auto-reload? on page 265). the timer 1 reload value should be set so that overflows will occur at two times the desired uart baud rate freq uency. timer 1 may be clocked by one of six sources: sysclk, sysclk/4, sysclk/12, sysclk/48, the external oscillator clock/8, or an external input t1. for any given timer 1 clock source, the uart0 baud rate is determined by equation 32.1-a and equation 32.1-b. equation 32.1. uart0 baud rate where t1 clk is the frequency of the clock supplied to timer 1, and t1h is the high byte of timer 1 (reload value). timer 1 clock frequency is selected as descri bed in section ?33. timers? on page 262. a quick ref- erence for typical baud rates and system clock frequencies is given in table 32.1 through table 32.2. the internal oscillator may st ill generate the system clock when the external oscillator is driving timer 1. rx timer start detected overflow overflow th1 tl1 tx clock 2 rx clock 2 timer 1 uart uartbaudrate 1 2 -- - t1_overflow_rate ? = t1_overflow_rate t1 clk 256 th1 ? ------------------------- - = a) b) c8051f70x/71x 256 rev. 1.0 32.2. operational modes uart0 provides standard asynchronous, full duplex communication. the uart mode (8-bit or 9-bit) is selected by the s0mode bit (sco n0.7). typical uart connection options are shown in figure 32.3. figure 32.3. uart interconnect diagram 32.2.1. 8-bit uart 8-bit uart mode uses a total of 10 bits per data byte: one start bit, eight data bits (lsb first), and one stop bit. data are transmitted lsb first from the tx0 pin and received at the rx0 pin. on receive, the eight data bits are stored in sbuf0 and the stop bit goes into rb80 (scon0.2). data transmission begins wh en software writes a data byte to th e sbuf0 register. the ti0 transmit inter- rupt flag (scon0.1) is set at the end of the transmi ssion (the beginning of the st op-bit time). data recep- tion can begin any time after the re n0 receive enable bit (scon0.4) is set to logic 1. after the stop bit is received, the data byte w ill be loaded into the sbuf0 re ceive register if the follo wing conditions are met: ri0 must be logic 0, and if mce0 is logic 1, the stop bit must be logic 1. in the event of a receive data over- run, the first received 8 bits are la tched into the sbuf0 receive register and the following overrun data bits are lost. if these conditions are met, the eight bits of data is stored in sbuf0, the stop bit is stored in rb80 and the ri0 flag is set. if these conditio ns are not met, sbuf0 and rb80 will no t be loaded and the ri0 flag will not be set. an interrupt will occur if enabled when ei ther ti0 or ri0 is set. figure 32.4. 8-bit uart timing diagram or rs-232 c8051xxxx rs-232 level xltr tx rx c8051xxxx rx tx mcu rx tx d1 d0 d2 d3 d4 d5 d6 d7 start bit mark stop bit bit times bit sampling space rev. 1.0 257 c8051f70x/71x 32.2.2. 9-bit uart 9-bit uart mode uses a total of eleven bits per data byte: a start bit, 8 data bits (lsb first), a programma- ble ninth data bit, and a stop bit. the state of the nint h transmit data bit is determ ined by the value in tb80 (scon0.3), which is assigned by user software. it can be assigned the value of the parity flag (bit p in reg- ister psw) for error detection, or used in multiprocessor communications. on receive, the ninth data bit goes into rb80 (scon0.2) and the stop bit is ignored. data transmission begins when an instruction writes a data byte to the sbuf0 register. the ti0 transmit interrupt flag (scon0.1) is set at the end of the tran smission (the beginning of the stop-bit time). data reception can begin any time after the ren0 receive enab le bit (scon0.4) is set to 1. after the stop bit is received, the data byte w ill be loaded into the sbuf0 re ceive register if the follo wing conditions are met: (1) ri0 must be logic 0, and (2) if mce0 is logic 1, the 9th bit must be logic 1 (when mce0 is logic 0, the state of the ninth data bit is unimportant). if these co nditions are met, the eight bits of data are stored in sbuf0, the ninth bit is stored in rb80, and the ri0 fl ag is set to 1. if the above conditions are not met, sbuf0 and rb80 will not be loaded and the ri0 flag will not be set to 1. a ua rt0 interrupt will occur if enabled when either ti0 or ri0 is set to 1. figure 32.5. 9-bit uart timing diagram d1 d0 d2 d3 d4 d5 d6 d7 start bit mark stop bit bit times bit sampling space d8 c8051f70x/71x 258 rev. 1.0 32.3. multiprocessor communications 9-bit uart mode supports multiprocessor communication between a master processor and one or more slave processors by special use of the ninth data bit. when a master processor wants to transmit to one or more slaves, it first sends an address byte to select the target(s). an address byte differs from a data byte in that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0. setting the mce0 bit (scon0.5) of a slave processor configures its uart such that when a stop bit is received, the uart will generat e an interrupt only if the ninth bit is logic 1 (rb80 = 1) signifying an address byte has been received. in the uart interrupt handler, software will compare the receiv ed address with the slave's own assigned 8-bit addre ss. if the addresses match, the slave will clear its mce0 bit to enable interrupts on the reception of the following data byte (s). slaves that weren't addressed leave their mce0 bits set and do not generate interrupts on the reception of the following data bytes, thereby ignoring the data. once the entire message is rece ived, the addressed slave resets its mce0 bit to ignore all transmis- sions until it receives the next address byte. multiple addresses can be assigned to a single sl ave and/or a single address can be assigned to multiple slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. the master processor can be configured to receive all transmissi ons or a protocol can be implemented such that the master/slave role is tem porarily reversed to enable half-duplex transmission between the original master and slave(s). figure 32.6. uart multi-processor mode interconnect diagram master device slave device tx rx rx tx slave device rx tx slave device rx tx v+ rev. 1.0 259 c8051f70x/71x sfr address = 0x98; sfr page = all pages; bit-addressable sfr definition 32.1. scon0: serial port 0 control bit76543210 name s0mode mce0 ren0 tb80 rb80 ti0 ri0 type r/w r r/w r/w r/w r/w r/w r/w reset 01000000 bit name function 7s0mode serial port 0 operation mode. selects the uart0 operation mode. 0: 8-bit uart with variable baud rate. 1: 9-bit uart with variable baud rate. 6 unused read = 1b, write = don?t care. 5mce0 multiprocessor comm unication enable. the function of this bit is dependent on the serial port 0 operation mode: mode 0: checks for valid stop bit. 0: logic level of stop bit is ignored. 1: ri0 will only be activated if stop bit is logic level 1. mode 1: multiprocessor communications enable. 0: logic level of ninth bit is ignored. 1: ri0 is set and an interrupt is genera ted only when the ninth bit is logic 1. 4ren0 receive enable. 0: uart0 reception disabled. 1: uart0 reception enabled. 3tb80 ninth transmission bit. the logic level of this bit will be sent as the ninth transmission bi t in 9-bit uart mode (mode 1). unused in 8-bit mode (mode 0). 2rb80 ninth receive bit. rb80 is assigned the value of the stop bit in mode 0; it is assigned the value of the 9th data bit in mode 1. 1ti0 transmit interrupt flag. set by hardware when a byte of data has been transmitted by uart0 (after the 8th bit in 8-bit uart mode, or at the beginning of the stop bit in 9-bit uart mode). when the uart0 interrupt is enabled, setting this bit causes the cpu to vector to the uart0 interrupt service routine. this bit must be cleared manually by software. 0ri0 receive interrupt flag. set to 1 by hardware when a byte of data has been received by uart0 (set at the stop bit sampling time). when the uart0 in terrupt is enabled, setting this bit to 1 causes the cpu to vector to the uart0 in terrupt service routine. this bit must be cleared manually by software. c8051f70x/71x 260 rev. 1.0 sfr address = 0x99; sfr page = all pages sfr definition 32.2. sbuf0: seri al (uart0) port data buffer bit76543210 name sbuf0[7:0] type r/w reset 00000000 bit name function 7:0 sbuf0[7:0] serial data buffer bits 7?0 (msb?lsb). this sfr accesses two registers; a transmit shift register and a receive latch register. when data is written to sbuf0, it goes to the transmit shift register and is held for serial transmission. writing a byte to sbuf0 initiates the transmission. a read of sbuf0 returns the contents of the receive latch. rev. 1.0 261 c8051f70x/71x table 32.1. timer settings for standard baud rates using the internal 24.5 mhz oscillator frequency: 24.5 mhz target baud rate (bps) baud rate% error oscillator divide factor timer clock source sca1?sca0 (pre-scale select) 1 t1m 1 timer 1 reload value (hex) sysclk from internal osc. 230400 ?0.32% 106 sysclk xx 2 1 0xcb 115200 ?0.32% 212 sysclk xx 1 0x96 57600 0.15% 426 sysclk xx 1 0x2b 28800 ?0.32% 848 sysclk/4 01 0 0x96 14400 0.15% 1704 sysclk/12 00 0 0xb9 9600 ?0.32% 2544 sysclk/12 00 0 0x96 2400 ?0.32% 10176 sysclk/48 10 0 0x96 1200 0.15% 20448 sysclk/48 10 0 0x2b notes: 1. sca1 ? sca0 and t1m bit definitions can be found in section 33.1 . 2. x = don?t care. table 32.2. timer settings for standard baud rates using an external 22.1184 mhz oscillator frequency: 22.1184 mhz target baud rate (bps) baud rate% error oscillator divide factor timer clock source sca1?sca0 (pre-scale select) 1 t1m 1 timer 1 reload value (hex) sysclk from external osc. 230400 0.00% 96 sysclk xx 2 10xd0 115200 0.00% 192 sysclk xx 1 0xa0 57600 0.00% 384 sysclk xx 1 0x40 28800 0.00% 768 sysclk / 12 00 0 0xe0 14400 0.00% 1536 sysclk / 12 00 0 0xc0 9600 0.00% 2304 sysclk / 12 00 0 0xa0 2400 0.00% 9216 sysclk / 48 10 0 0xa0 1200 0.00% 18432 sysc lk / 48 10 0 0x40 sysclk from internal osc. 230400 0.00% 96 extclk / 8 11 0 0xfa 115200 0.00% 192 extclk / 8 11 0 0xf4 57600 0.00% 384 extclk / 8 11 0 0xe8 28800 0.00% 768 extclk / 8 11 0 0xd0 14400 0.00% 1536 extclk / 8 11 0 0xa0 9600 0.00% 2304 extclk / 8 11 0 0x70 notes: 1. sca1 ? sca0 and t1m bit definitions can be found in section 33.1 . 2. x = don?t care. c8051f70x/71x 262 rev. 1.0 33. timers each mcu includes four counter/timers: two are 16-bit counter/timers compatible with those found in the standard 8051, and two are 16-bit auto-reload timer fo r use with the adc, smbus, or for general purpose use. these timers can be used to measure time in tervals, count external events and generate periodic interrupt requests. timer 0 and timer 1 are nearly identical and have four primary modes of operation. timer 2 and timer 3 offer 16-bit and split 8-bit time r functionality with auto-reload. additionally, timer 3 offers the ability to be clocked from the external oscillator while the dev ice is in suspend mode, and can be used as a wake-up source. this allows for implem entation of a very low-power system, including rtc capability. timers 0 and 1 may be clocked by one of five source s, determined by the timer mode select bits (t1m ? t0m) and the clock scale bits (sca1 ? sca0). the clock scale bits define a pre-scaled clock from which timer 0 and/or timer 1 may be clocked (see sfr definition 33.1 for pre-scaled clock selection). timer 0/1 may then be configured to use this pre-sc aled clock signal or the system clock. timer 2 and timer 3 may be clocked by the system clock, the system clock divided by 12, or the external oscillator clock source divided by 8. timer 0 and timer 1 may also be operated as counte rs. when functioning as a counter, a counter/timer register is incremented on each high-to-low transition at the selected input pin (t0 or t1). events with a fre- quency of up to one-fourth the system clock frequency can be counted. the input signal need not be peri- odic, but it should be held at a gi ven level for at least two full system clock cycles to ensure the level is properly sampled. timer 0 and timer 1 modes: ti mer 2 modes: timer 3 modes: 13-bit counter/timer 16-bit timer with auto-reload 16-bit timer with auto-reload 16-bit counter/timer 8-bit counter/timer with auto-reload two 8-bit timers with auto-reload t wo 8-bit timers with auto-reload two 8-bit counter/timers (timer 0 only) rev. 1.0 263 c8051f70x/71x sfr address = 0x8e; sfr page = all pages sfr definition 33.1. ckcon: clock control bit76543210 name t3mh t3ml t2mh t2ml t1m t0m sca[1:0] type r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7t3mh timer 3 high byte clock select. selects the clock supplied to the timer 3 high byte (split 8-bit timer mode only). 0: timer 3 high byte uses the clock defined by the t3xclk bit in tmr3cn. 1: timer 3 high byte uses the system clock. 6t3ml timer 3 low byte clock select. selects the clock supplied to timer 3. selects the clock supplied to the lower 8-bit timer in split 8-bit timer mode. 0: timer 3 low byte uses the clock defined by the t3xclk bit in tmr3cn. 1: timer 3 low byte uses the system clock. 5t2mh timer 2 high byte clock select. selects the clock supplied to the timer 2 high byte (split 8-bit timer mode only). 0: timer 2 high byte uses the clock defined by the t2xclk bit in tmr2cn. 1: timer 2 high byte uses the system clock. 4t2ml timer 2 low byte clock select. selects the clock supplied to timer 2. if timer 2 is configured in split 8-bit timer mode, this bit selects the clock supp lied to the lower 8-bit timer. 0: timer 2 low byte uses the clock defined by the t2xclk bit in tmr2cn. 1: timer 2 low byte uses the system clock. 3t1 timer 1 clock select. selects the clock source supplied to timer 1. ignored when c/t1 is set to 1. 0: timer 1 uses the clock defined by the prescale bits sca[1:0]. 1: timer 1 uses the system clock. 2t0 timer 0 clock select. selects the clock source supplied to timer 0. ignored when c/t0 is set to 1. 0: counter/timer 0 uses the clock defi ned by the prescale bits sca[1:0]. 1: counter/timer 0 uses the system clock. 1:0 sca[1:0] timer 0/1 prescale bits. these bits control the timer 0/1 clock prescaler: 00: system clock divided by 12 01: system clock divided by 4 10: system clock divided by 48 11: external clock divided by 8 (synchronized with the system clock) c8051f70x/71x 264 rev. 1.0 33.1. timer 0 and timer 1 each timer is implemented as a 16-bit register acce ssed as two separate bytes: a low byte (tl0 or tl1) and a high byte (th0 or th1). the counter/timer cont rol register (tcon) is used to enable timer 0 and timer 1 as well as indicate status. timer 0 interrupts can be enabled by setting the et0 bit in the ie regis- ter (section ?21.2. interrupt register descriptions? on page 140); timer 1 interrupts can be enabled by set- ting the et1 bit in the ie register (section ?21. 2. interrupt register descriptions? on page 140). both counter/timers operate in one of four primary m odes selected by setting the mode select bits t1m1 ? t0m0 in the counter/timer mode register (tmod). each timer can be configured independently. each operating mode is described below. 33.1.1. mode 0: 13 -bit counter/timer timer 0 and timer 1 operate as 13-bit counter/timers in mode 0. the following describes the configuration and operation of timer 0. however, both timers operate identically, and timer 1 is configured in the same manner as described for timer 0. the th0 register holds the eight msbs of the 13-bit c ounter/timer. tl0 holds the five lsbs in bit positions tl0.4 ? tl0.0. the three upper bits of tl0 (tl0.7 ? tl0.5) are indeterminate a nd should be masked out or ignored when reading. as the 13-bit timer register increments and overflows from 0x1fff (all ones) to 0x0000, the timer overflow flag tf0 in tcon is set and an interrupt will occur if timer 0 interrupts are enabled. the c/t0 bit in the tmod register selects the counte r/timer's clock source. when c/t0 is set to logic 1, high-to-low transitions at the selected timer 0 input pi n (t0) increment the timer register (refer to section ?28.3. priority crossbar decoder? on page 185 for information on selecting and configuring external i/o pins). clearing c/t selects the clock defined by the t0 m bit in register ckcon. when t0m is set, timer 0 is clocked by the system clock. when t0m is cleared, timer 0 is clocke d by the source selected by the clock scale bits in ckcon (see sfr definition 33.1). setting the tr0 bit (tcon.4) enables the timer when eit her gate0 in the tmod register is logic 0 or the input signal int0 is active as defined by bit in0pl in register it01cf (see sfr definition 21.7). setting gate0 to 1 allows the timer to be controlled by the external input signal int0 (see section ?21.2. interrupt register descriptions? on page 140), facilitating pulse width measurements setting tr0 does not force the timer to reset. the timer registers should be loaded with the desired initial value before the timer is enabled. tl1 and th1 form the 13-bit register for timer 1 in the same manner as described above for tl0 and th0. timer 1 is configured and controlled using the releva nt tcon and tmod bits just as with timer 0. the input signal int1 is used with timer 1; the int1 polarity is defined by bit in1pl in register it01cf (see sfr definition 21.7). tr0 gate0 int0 counter/timer 0 x x disabled 1 0 x enabled 1 1 0 disabled 1 1 1 enabled note: x = don't care rev. 1.0 265 c8051f70x/71x figure 33.1. t0 mode 0 block diagram 33.1.2. mode 1: 16 -bit counter/timer mode 1 operation is the same as mode 0, except that the counter/timer registers use all 16 bits. the coun- ter/timers are enabled and configured in mode 1 in the same manner as for mode 0. 33.1.3. mode 2: 8-bit counter/timer with auto-reload mode 2 configures timer 0 and timer 1 to operate as 8-bi t counter/timers with auto matic reload of the start value. tl0 holds the count and th0 holds the reload va lue. when the counter in tl0 overflows from all ones to 0x00, the timer overflow fl ag tf0 in the tcon register is set and the counter in tl0 is reloaded from th0. if timer 0 interrupts ar e enabled, an interr upt will occur when the tf0 flag is set. the reload value in th0 is not changed. tl0 must be initialized to the desired value before enabling the timer for the first count to be correct. when in mode 2, timer 1 operates identically to timer 0. both counter/timers are enabled and configured in mode 2 in the same manner as mode 0. setting the tr0 bit (tcon.4) enables the timer when either gate0 in the tmod regi ster is logic 0 or when the input signal int0 is active as defined by bit in0pl in register it01cf (see section ?21.3. int0 and int1 external interrupts? on page 146 for details on the external input signals int0 and int1 ). tclk tl0 (5 bits) th0 (8 bits) tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt tr0 0 1 0 1 sysclk pre-scaled clock tmod t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 gate0 int0 t0 crossbar it01cf i n 1 s l 1 i n 1 s l 0 i n 1 s l 2 i n 1 p l i n 0 p l i n 0 s l 2 i n 0 s l 1 i n 0 s l 0 in0pl xor t0m c8051f70x/71x 266 rev. 1.0 figure 33.2. t0 mode 2 block diagram 33.1.4. mode 3: two 8-bit counter/timers (timer 0 only) in mode 3, timer 0 is configured as two separate 8-bit counter/timers held in tl0 and th0. the coun- ter/timer in tl0 is controlled using the timer 0 control/status bits in tcon and tmod: tr0, c/t0, gate0 and tf0. tl0 can use either the system clock or an ex ternal input signal as its timebase. the th0 register is restricted to a timer function so urced by the system clock or presca led clock. th0 is enabled using the timer 1 run control bit tr1. th0 sets the timer 1 ov erflow flag tf1 on overflow and thus controls the timer 1 interrupt. timer 1 is inactive in mode 3. when timer 0 is op erating in mode 3, timer 1 can be operated in modes 0, 1 or 2, but cannot be clocked by external signals nor set the tf1 flag and generate an interrupt. however, the timer 1 overflow can be used to generate baud rates or overflow conditions for other peripherals. while timer 0 is operating in mode 3, timer 1 run control is handled through its mode settings. to run timer 1 while timer 0 is in mode 3, set the timer 1 mode as 0, 1, or 2. to disable timer 1, configure it for mode 3. tclk tmod t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt tl0 (8 bits) reload th0 (8 bits) 0 1 0 1 sysclk pre-scaled clock it01cf i n 1 s l 1 i n 1 s l 0 i n 1 s l 2 i n 1 p l i n 0 p l i n 0 s l 2 i n 0 s l 1 i n 0 s l 0 tr0 gate0 in0pl xor int0 t0 crossbar t0m rev. 1.0 267 c8051f70x/71x figure 33.3. t0 mode 3 block diagram tl0 (8 bits) tmod 0 1 tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt interrupt 0 1 sysclk pre-scaled clock tr1 th0 (8 bits) t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 tr0 gate0 in0pl xor int0 t0 crossbar t0m c8051f70x/71x 268 rev. 1.0 sfr address = 0x88; sfr page = all pages; bit-addressable sfr definition 33.2. tcon: timer control bit76543210 name tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7 tf1 timer 1 overflow flag. set to 1 by hardware when timer 1 overflows. this flag can be cleared by software but is automatically cleared when the cpu vectors to the timer 1 interrupt service routine. 6tr1 timer 1 run control. timer 1 is enabled by setting this bit to 1. 5 tf0 timer 0 overflow flag. set to 1 by hardware when timer 0 overflows. this flag can be cleared by software but is automatically cleared when the cpu vectors to the timer 0 interrupt service routine. 4tr0 timer 0 run control. timer 0 is enabled by setting this bit to 1. 3ie1 external interrupt 1. this flag is set by hardware when an edge/l evel of type defined by it1 is detected. it can be cleared by software but is automatically cleared when the cpu vectors to the external interrupt 1 service routine in edge-triggered mode. 2it1 interrupt 1 type select. this bit selects whether the configured /int 1 interrupt will be edge or level sensitive. /int1 is configured active low or high by the in1pl bit in the it01cf register (see sfr definition 21.7). 0: /int1 is level triggered. 1: /int1 is edge triggered. 1ie0 external interrupt 0. this flag is set by hardware when an edge/l evel of type defined by it1 is detected. it can be cleared by software but is automatically cleared when the cpu vectors to the external interrupt 0 service routine in edge-triggered mode. 0it0 interrupt 0 type select. this bit selects whether the configured int0 interrupt will be edge or level sensitive. int0 is configured active low or high by the in0pl bit in register it01cf (see sfr definition 21.7). 0: int0 is level triggered. 1: int0 is edge triggered. rev. 1.0 269 c8051f70x/71x sfr address = 0x89; sfr page = all pages sfr definition 33.3. tmod: timer mode bit76543210 name gate1 c/t1 t1m[1:0] gate0 c/t0 t0m[1:0] type r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7gate1 timer 1 gate control. 0: timer 1 enabled when tr1 = 1 irrespective of int1 logic level. 1: timer 1 enabled only when tr1 = 1 and int1 is active as defined by bit in1pl in register it01cf (see sfr definition 21.7). 6c/t1 counter/timer 1 select. 0: timer: timer 1 incremented by clock defined by t1m bit in register ckcon. 1: counter: timer 1 incremented by high -to-low transitions on external pin (t1). 5:4 t1m[1:0] timer 1 mode select. these bits select the timer 1 operation mode. 00: mode 0, 13-bit counter/timer 01: mode 1, 16-bit counter/timer 10: mode 2, 8-bit counter/timer with auto-reload 11: mode 3, timer 1 inactive 3gate0 timer 0 gate control. 0: timer 0 enabled when tr0 = 1 irrespective of int0 logic level. 1: timer 0 enabled only when tr0 = 1 and int0 is active as defined by bit in0pl in register it01cf (see sfr definition 21.7). 2c/t0 counter/timer 0 select. 0: timer: timer 0 incremented by clock defined by t0m bit in register ckcon. 1: counter: timer 0 incremented by high -to-low transitions on external pin (t0). 1:0 t0m[1:0] timer 0 mode select. these bits select the timer 0 operation mode. 00: mode 0, 13-bit counter/timer 01: mode 1, 16-bit counter/timer 10: mode 2, 8-bit counter/timer with auto-reload 11: mode 3, two 8-bit counter/timers c8051f70x/71x 270 rev. 1.0 sfr address = 0x8a; sfr page = all pages sfr address = 0x8b; sfr page = all pages sfr definition 33.4. tl0: timer 0 low byte bit76543210 name tl0[7:0] type r/w reset 00000000 bit name function 7:0 tl0[7:0] timer 0 low byte. the tl0 register is the low byte of the 16-bit timer 0. sfr definition 33.5. tl1: timer 1 low byte bit76543210 name tl1[7:0] type r/w reset 00000000 bit name function 7:0 tl1[7:0] timer 1 low byte. the tl1 register is the low byte of the 16-bit timer 1. rev. 1.0 271 c8051f70x/71x sfr address = 0x8c; sfr page = all pages sfr address = 0x8d; sfr page = all pages sfr definition 33.6. th0 : timer 0 high byte bit76543210 name th0[7:0] type r/w reset 00000000 bit name function 7:0 th0[7:0] timer 0 high byte. the th0 register is the high byte of the 16-bit timer 0. sfr definition 33.7. th1 : timer 1 high byte bit76543210 name th1[7:0] type r/w reset 00000000 bit name function 7:0 th1[7:0] timer 1 high byte. the th1 register is the high byte of the 16-bit timer 1. c8051f70x/71x 272 rev. 1.0 33.2. timer 2 timer 2 is a 16-bit timer formed by two 8-bit sfrs: tmr2l (low byte) and tmr2h (high byte). timer 2 may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. the t2split bit (tmr2cn.3) defines the timer 2 operation mode. timer 2 can also be used in capture mode to capture rising edges of the comparator 0 output. timer 2 may be clocked by the system clock, the syst em clock divided by 12, or the external oscillator source divided by 8. the external clock mode is ideal for real-time clock (rtc) functionality, where the internal oscillator drives t he system clock while timer 2 (and/or the pca) is clocked by an external preci- sion oscillator. the external oscillator source divided by 8 is synchronized with the system clock. 33.2.1. 16-bit time r with auto-reload when t2split (tmr2cn.3) is zero, timer 2 operates as a 16-bit timer with au to-reload. timer 2 can be clocked by sysclk, sysclk divided by 12, or the exte rnal oscillator clock source divided by 8. as the 16-bit timer register increments and overflows from 0xffff to 0x0000, the 16 -bit value in the timer 2 reload registers (tmr2rlh and tmr2rll) is loaded in to the timer 2 register as shown in figure 33.4, and the timer 2 high byte overflow flag (tmr2cn.7) is set. if timer 2 interrupts are enabled (if ie.5 is set), an interrupt will be generated on each timer 2 overflow. additionally , if timer 2 interrupts are enabled and the tf2len bit is set (tmr2cn. 5), an interr upt will be generated each time the lower 8 bits (tmr2l) overflow from 0xff to 0x00. figure 33.4. timer 2 16-bit mode block diagram external clock / 8 sysclk / 12 sysclk tmr2l tmr2h tmr2rll tmr2rlh reload tclk 0 1 tr2 tmr2cn t2split tf2cen tf2l tf2h t2xclk tr2 0 1 t2xclk interrupt tf2len to adc, smbus to smbus tl2 overflow ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m rev. 1.0 273 c8051f70x/71x 33.2.2. 8-bit timers with auto-reload when t2split is set, timer 2 operates as two 8-bi t timers (tmr2h and tmr2l). both 8-bit timers oper- ate in auto-reload mode as shown in figure 33.5. tmr2rll holds the reload value for tmr2l; tmr2rlh holds the reload value for tmr2h. the tr2 bit in tmr2cn handles the run control for tmr2h. tmr2l is always running when configured for 8-bit mode. each 8-bit timer may be c onfigured to use sysclk, sysclk divided by 12, or the external oscillator clock source divided by 8. the timer 2 clock select bits (t2mh and t2ml in ckcon) select either sysclk or the clock defined by the timer 2 external cloc k select bit (t2xclk in tmr2cn), as follows: the tf2h bit is set when tmr2h overflows from 0xff to 0x00; the tf2l bit is set when tmr2l overflows from 0xff to 0x00. when timer 2 interrupts are enabled (ie.5), an interrupt is generated each time tmr2h overflows. if timer 2 interrupts are enabled an d tf2len (tmr2cn.5) is set, an interrupt is gener- ated each time either tmr2l or tmr2h overflows. when tf2len is enabled, software must check the tf2h and tf2l flags to determine the source of the timer 2 interrupt. the tf2h and tf2l interrupt flags are not cleared by hardware and must be manually cleared by software. figure 33.5. timer 2 8-bit mode block diagram t2mh t2xclk tmr2h clock source t2ml t2xclk tmr2l clock source 0 0 sysclk / 12 0 0 sysclk / 12 0 1 external clock / 8 0 1 external clock / 8 1 x sysclk 1 x sysclk sysclk tclk 0 1 tr2 external clock / 8 sysclk / 12 0 1 t2xclk 1 0 tmr2h tmr2rlh reload reload tclk tmr2l tmr2rll interrupt tmr2cn t2split tf2cen tf2len tf2l tf2h t2xclk tr2 to adc, smbus to smbus ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m c8051f70x/71x 274 rev. 1.0 33.2.3. comparator 0 capture mode the capture mode in timer 2 allows comparator 0 rising edges to be captured with the timer clocking from the system clock or the system clock divided by 12 . timer 2 capture mode is enabled by setting tf2cen to 1 and t2split to 0. when capture mode is enabled, a capture event will be generated on every comparator 0 rising edge. when the capture event occurs, the contents of timer 2 (tmr2h:tmr2l) are loaded into the timer 2 reload registers (tmr2rlh:tmr2rll) and the tf2h flag is set (triggering an interrupt if timer 2 inter- rupts are enabled). by recording the difference between two successive timer capture values, the comparator 0 period can be determined with respect to the timer 2 clock. the timer 2 clock should be much faster than the capture clock to achieve an accurate reading. this mode allows software to de termine the time between consecutiv e comparator 0 rising edges, which can be used for detecting changes in the capacitance of a capacitive switch, or measuring the frequency of a low-level analog signal. figure 33.6. timer 2 capture mode block diagram sysclk 0 1 ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m tmr2l tmr2h tclk tr2 tmr2rll tmr2rlh capture tmr2cn t2split tf2cen tf2l tf2h t2xclk tr2 tf2len tf2cen interrupt sysclk / 12 t2xclk external clock / 8 comparator 0 output 0 1 rev. 1.0 275 c8051f70x/71x sfr address = 0xc8; sfr page = all pages; bit-addressable sfr definition 33.8. tmr 2cn: timer 2 control bit76543210 name tf2h tf2l tf2len tf2cen t2split tr2 t2xclk type r/w r/w r/w r/w r/w r/w r r/w reset 00000000 bit name function 7 tf2h timer 2 high byte overflow flag. set by hardware when the timer 2 high byte overflows from 0xff to 0x00. in 16 bit mode, this will occur when timer 2 overflows from 0x ffff to 0x0000. when the timer 2 interrupt is enabled, setting this bi t causes the cpu to vector to the timer 2 interrupt service routine. this bit is not automatically cleared by hardware. 6 tf2l timer 2 low byte overflow flag. set by hardware when the timer 2 low byte overflows from 0xff to 0x00. tf2l will be set when the low byte overflows regardless of the timer 2 mode. this bit is not automatically cleared by hardware. 5 tf2len timer 2 low byte interrupt enable. when set to 1, this bit enables timer 2 lo w byte interrupts. if ti mer 2 interrupts are also enabled, an in terrupt will be ge nerated when the low byte of timer 2 overflows. 4tf2cen timer 2 comparator capture enable. when set to 1, this bit enables timer 2 comparator capture mode. if tf2cen is set, on a rising edge of the comparator0 output the current 16-bit timer value in tmr2h:tmr2l will be copied to tmr2rlh:tmr2 rll. if timer 2 interrupts are also enabled, an interrupt will be generated on this event. 3 t2split timer 2 split mode enable. when this bit is set, timer 2 operates as two 8-bit timers with auto-reload. 0: timer 2 operates in 16-bit auto-reload mode. 1: timer 2 operates as tw o 8-bit auto-reload timers. 2tr2 timer 2 run control. timer 2 is enabled by setting this bit to 1. in 8-bit mode, this bit enables/disables tmr2h only; tmr2l is alwa ys enabled in split mode. 1 unused read = 0b; write = don?t care. 0t2xclk timer 2 external clock select. this bit selects the external clock source fo r timer 2. if timer 2 is in 8-bit mode, this bit selects the external oscillator clock so urce for both timer bytes. however, the timer 2 clock select bits (t2mh and t2ml in register ckcon) may still be used to select between the external clock an d the system clock for either timer. 0: timer 2 clock is the system clock divided by 12. 1: timer 2 clock is the external clo ck divided by 8 (syn chronized with sysclk). c8051f70x/71x 276 rev. 1.0 sfr address = 0xca; sfr page = 0 sfr address = 0xcb; sfr page = 0 sfr definition 33.9. tmr2rll: time r 2 reload register low byte bit76543210 name tmr2rll[7:0] type r/w reset 00000000 bit name function 7:0 tmr2rll[7:0] timer 2 reload register low byte. tmr2rll holds the low byte of the reload value for timer 2. sfr definition 33.10. tmr2rlh: ti mer 2 reload register high byte bit76543210 name tmr2rlh[7:0] type r/w reset 00000000 bit name function 7:0 tmr2rlh[7:0] timer 2 reload register high byte. tmr2rlh holds the high byte of the reload value for timer 2. rev. 1.0 277 c8051f70x/71x sfr address = 0xcc; sfr page = 0 sfr address = 0xcd; sfr page = 0 sfr definition 33.11. tmr2l: timer 2 low byte bit76543210 name tmr2l[7:0] type r/w reset 00000000 bit name function 7:0 tmr2l[7:0] timer 2 low byte. in 16-bit mode, the tmr2l register contains the low byte of the 16-bit timer 2. in 8- bit mode, tmr2l contains the 8-bit low byte timer value. sfr definition 33.12. tmr2h timer 2 high byte bit76543210 name tmr2h[7:0] type r/w reset 00000000 bit name function 7:0 tmr2h[7:0] timer 2 low byte. in 16-bit mode, the tmr2h register contains the high byte of the 16-bit timer 2. in 8- bit mode, tmr2h contains the 8-bit high byte timer value. c8051f70x/71x 278 rev. 1.0 33.3. timer 3 timer 3 is a 16-bit timer formed by two 8-bit sfrs: tmr3l (low byte) and tmr3h (high byte). timer 3 may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. the t3split bit (tmr3cn.3) defines the timer 3 operation mode. timer 3 may be clocked by the system clock, the system clock divided by 12, or the external oscillator source divided by 8. the external clock mode is ideal for real-time clock (rtc) functionality, where the internal high-fr equency oscillator drives the system clock while timer 3 is clocked by an external oscillator source. the external oscillator sour ce divided by 8 is synchronized wit h the system clock when in all oper- ating modes except suspend. when the internal oscillato r is placed in suspend mode, the external clock/8 signal can directly drive the timer. this allows the use of an external cl ock to wake up the device from sus- pend mode. the timer will continue to run in suspend mode and count up. when the timer overflow occurs, the device will wake from suspend mode, and begin executing code again. t he timer value may be set prior to entering suspend, to overflow in the desired amount of time (number of clocks) to wake the device. if a wake-up source other than the timer wakes the de vice from suspen d mode, it may take up to three timer clocks before the timer registers can be read or written. during this time , the stsync bit in register oscicn will be set to 1, to indicate that it is not safe to read or write the timer registers. 33.3.1. 16-bit time r with auto-reload when t3split (tmr3cn.3) is zero, timer 3 operates as a 16-bit timer with auto-reload. timer 3 can be clocked by sysclk, sysclk divided by 12, or the exte rnal oscillator clock source divided by 8. as the 16-bit timer register increments and overflows from 0xffff to 0x0000, the 16-bit value in the timer 3 reload registers (tmr3rlh and tmr3rll) is loaded in to the timer 3 register as shown in figure 33.7, and the timer 3 high byte overflow fl ag (tmr3cn.7) is set. if timer 3 interrupts are enabled (if eie1.7 is set), an interrupt will be generat ed on each timer 3 overflow. addition ally, if timer 3 in terrupts are enabled and the tf3len bit is set (tmr3cn. 5), an interr upt will be generated each time the lower 8 bits (tmr3l) overflow from 0xff to 0x00. figure 33.7. timer 3 16-bit mode block diagram sysclk tmr3l tmr3h tmr3rll tmr3rlh reload tclk 0 1 tr3 tmr3cn t3split tf3cen tf3l tf3h t3xclk tr3 interrupt tf3len to adc ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m external clock / 8 sysclk / 12 t3xclk 0 1 rev. 1.0 279 c8051f70x/71x 33.3.2. 8-bit timers with auto-reload when t3split is set, timer 3 operates as two 8-bi t timers (tmr3h and tmr3l). both 8-bit timers oper- ate in auto-reload mode as shown in figure 33.8. tmr3rll holds the reload value for tmr3l; tmr3rlh holds the reload value for tmr3h. the tr3 bit in tmr3cn handles the run control for tmr3h. tmr3l is always running when configured for 8-bit mode. timer 3 can also be used in capture mode to capture rising edges of the comparator 0 output. each 8-bit timer may be c onfigured to use sysclk, sysclk divided by 12, or the external oscillator clock source divided by 8. the timer 3 clock select bits (t3mh and t3ml in ckcon) select either sysclk or the clock defined by the timer 3 external clock select bits (t3xclk in tmr3cn), as follows: the tf3h bit is set when tmr3h overflows from 0xff to 0x00; the tf3l bit is set when tmr3l overflows from 0xff to 0x00. when timer 3 interrupts are enabled, an interrupt is generated each time tmr3h over- flows. if timer 3 interrupts are enabled and tf3len (tmr3cn.5) is set, an interrupt is generated each time either tmr3l or tmr3h overflows. when tf3le n is enabled, software must check the tf3h and tf3l flags to determine the source of the timer 3 interrupt. the tf3h and tf3l interrupt flags are not cleared by hardware and must be manually cleared by software. figure 33.8. timer 3 8-bit mode block diagram t3mh t3xclk tmr3h clock source t3ml t3xclk tmr3l clock source 0 0 sysclk / 12 0 0 sysclk / 12 0 1 external clock / 8 0 1 external clock / 8 1 x sysclk 1 x sysclk sysclk tclk 0 1 tr3 1 0 tmr3h tmr3rlh reload reload tclk tmr3l tmr3rll interrupt tmr3cn t3split tf3cen tf3len tf3l tf3h t3xclk tr3 to adc external clock / 8 sysclk / 12 t3xclk ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m 0 1 c8051f70x/71x 280 rev. 1.0 33.3.3. comparator 0 capture mode the capture mode in timer 3 allows comparator 0 rising edges to be captured with the timer clocking from the system clock or the system clock divided by 12 . timer 3 capture mode is enabled by setting tf3cen to 1 and t3split to 0. when capture mode is enabled, a capture event will be generated on every comparator 0 rising edge. when the capture event occurs, the contents of timer 3 (tmr3h:tmr3l) are loaded into the timer 3 reload registers (tmr3rlh:tmr3rll) and the tf3h flag is set (triggering an interrupt if timer 3 inter- rupts are enabled). by recording the difference between two successive timer capture values, the comparator 0 period can be determined with respect to the timer 3 clock. the timer 3 clock should be much faster than the capture clock to achieve an accurate reading. this mode allows software to de termine the time between consecutiv e comparator 0 rising edges, which can be used for detecting changes in the capacitance of a capacitive switch, or measuring the frequency of a low-level analog signal. figure 33.9. timer 3 capture mode block diagram sysclk 0 1 ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m tmr3l tmr3h tclk tr3 tmr3rll tmr3rlh capture tmr3cn t3split tf3cen tf3l tf3h t3xclk tr3 tf3len tf3cen interrupt sysclk / 12 t3xclk external clock / 8 comparator 0 output 0 1 rev. 1.0 281 c8051f70x/71x sfr address = 0x91; sfr page = 0 sfr definition 33.13. tm r3cn: timer 3 control bit76543210 name tf3h tf3l tf3len tf3cen t3split tr3 t3xclk type r/w r/w r/w r/w r/w r/w r r/w reset 00000000 bit name function 7 tf3h timer 3 high byte overflow flag. set by hardware when the timer 3 high byte overflows from 0xff to 0x00. in 16 bit mode, this will occur when timer 3 overflows from 0x ffff to 0x0000. when the timer 3 interrupt is enabled, setting this bit causes the cpu to vector to the timer 3 interrupt service routine. this bit is not automatically cleared by hardware. 6 tf3l timer 3 low byte overflow flag. set by hardware when the timer 3 low byte overflows from 0xff to 0x00. tf3l will be set when the low byte overflows regard less of the timer 3 mode. this bit is not automatically cleared by hardware. 5 tf3len timer 3 low byte interrupt enable. when set to 1, this bit enables timer 3 lo w byte interrupts. if ti mer 3 interrupts are also enabled, an in terrupt will be ge nerated when the low byte of timer 3 overflows. 4tf3cen timer 3 comparator capture enable. when set to 1, this bit enables timer 3 comparator capture mode. if tf3cen is set, on a rising edge of the comparator0 output the current 16-bit timer value in tmr3h:tmr3l will be copied to tmr3rlh:tmr3 rll. if timer 3 interrupts are also enabled, an interrupt will be generated on this event. 3 t3split timer 3 split mode enable. when this bit is set, timer 3 operates as two 8-bit timers with auto-reload. 0: timer 3 operates in 16-bit auto-reload mode. 1: timer 3 operates as tw o 8-bit auto-reload timers. 2tr3 timer 3 run control. timer 3 is enabled by setting this bit to 1. in 8-bit mode, this bit enables/disables tmr3h only; tmr3l is alwa ys enabled in split mode. 1 unused read = 0b; write = don?t care. 0t3xclk timer 3 external clock select. this bit selects the external clock source for timer 3. if timer 3 is in 8-bit mode, this bit selects the external oscillator clock so urce for both timer bytes. however, the timer 3 clock select bits (t3mh and t3ml in register ckcon) may still be used to select between the external clock an d the system clock for either timer. 0: system clock divided by 12. 1: external clock divided by 8 (synchro nized with sysclk when not in suspend). c8051f70x/71x 282 rev. 1.0 sfr address = 0x92; sfr page = 0 sfr address = 0x93; sfr page = 0 sfr definition 33.14. tmr3rll: ti mer 3 reload register low byte bit76543210 name tmr3rll[7:0] type r/w reset 00000000 bit name function 7:0 tmr3rll[7:0] timer 3 reload register low byte. tmr3rll holds the low byte of the reload value for timer 3. sfr definition 33.15. tmr3rlh: ti mer 3 reload register high byte bit76543210 name tmr3rlh[7:0] type r/w reset 00000000 bit name function 7:0 tmr3rlh[7:0] timer 3 reload register high byte. tmr3rlh holds the high byte of the reload value for timer 3. rev. 1.0 283 c8051f70x/71x sfr address = 0x94; sfr page = 0 sfr address = 0x95; sfr page = 0 sfr definition 33.16. tmr3l: timer 3 low byte bit76543210 name tmr3l[7:0] type r/w reset 00000000 bit name function 7:0 tmr3l[7:0] timer 3 low byte. in 16-bit mode, the tmr3l register contains the low byte of the 16-bit timer 3. in 8-bit mode, tmr3l contains the 8-bit low byte timer value. sfr definition 33.17. tmr3h timer 3 high byte bit76543210 name tmr3h[7:0] type r/w reset 00000000 bit name function 7:0 tmr3h[7:0] timer 3 high byte. in 16-bit mode, the tmr3h register contains the high byte of the 16-bit timer 3. in 8-bit mode, tmr3h contains the 8-bit high byte timer value. c8051f70x/71x 284 rev. 1.0 34. programmable counter array the programmable counter array (pca0) provides enhanced timer functionality while requiring less cpu intervention than the standard 8051 counter/timers. th e pca consists of a dedicated 16-bit counter/timer and three 16-bit capture/compare modules. each capt ure/compare module has its own associated i/o line (cexn) which is routed through the crossbar to port i/o when enabled. the counter/timer is driven by a programmable timebase that can select between seve n sources: system clock, system clock divided by four, system clock divided by twelve, the external osc illator clock source divided by 8, timer 0 overflows, or an external clock signal on the eci input pin. each capture/compare module may be configured to operate independently in one of six modes: edge-triggered capture, software timer, high-speed output, fre- quency output, 8 to 11-bit pwm, or 16-bit pwm (each mode is described in section ?34.3. capture/compare modules? on page 286). the external oscillator cl ock option is ideal for real-time clock (rtc) functionality, allowing the pca to be clocke d by a precision external oscillator while the inter- nal oscillator drives the system clock. the pca is co nfigured and controlled through the system controller's special function registers. the pca block diagram is shown in figure 34.1 figure 34.1. pca block diagram capture/compare module 1 capture/compare module 0 capture/compare module 2 cex1 eci crossbar cex2 cex0 port i/o 16-bit counter/timer pca clock mux sysclk/12 sysclk/4 timer 0 overflow eci sysclk external clock/8 rev. 1.0 285 c8051f70x/71x 34.1. pca counter/timer the 16-bit pca counter/timer consists of two 8-bi t sfrs: pca0l and pca0h. pca0h is the high byte (msb) of the 16-bit counter/timer and pca0l is the lo w byte (lsb). reading pc a0l automatically latches the value of pca0h into a ?snapshot? register; the following pca0h read accesses this ?snapshot? register. reading the pca0l register first guarantees an accu rate reading of the entire 16-bit pca0 counter. reading pca0h or pca0l does not disturb the counter operation. the cps2 ? cps0 bits in the pca0md register select the timebase for the counter/timer as shown in table 34.1. when the counter/timer overflows from 0xffff to 0x0 000, the counter overflow flag (cf) in pca0md is set to logic 1 and an interrupt request is generated if cf interrupts are enabled. setting the ecf bit in pca0md to logic 1 enables the cf flag to generate an interrupt request. the cf bit is not automatically cleared by hardware when the cpu vectors to the inte rrupt service routine, and must be cleared by soft- ware. clearing the cidl bit in the pca0md register a llows the pca to continue normal operation while the cpu is in idle mode. figure 34.2. pca counter/timer block diagram table 34.1. pca timebase input options cps2 cps1 cps0 timebase 0 0 0 system clock divided by 12 0 0 1 system clock divided by 4 0 1 0 timer 0 overflow 0 1 1 high-to-low transitions on eci (max rate = system clock divided by 4) 100system clock 1 0 1 external oscillator source divided by 8 * 1 1 x reserved note: external oscillator source divided by 8 is synchronized with the system clock. pca0cn c f c r c c f 0 c c f 2 c c f 1 pca0md c i d l e c f c p s 1 c p s 0 c p s 2 idle 0 1 pca0h pca0l snapshot register to sfr bus overflow to pca interrupt system cf pca0l read to pca modules sysclk/12 sysclk/4 timer 0 overflow eci 000 001 010 011 100 101 sysclk external clock/8 c8051f70x/71x 286 rev. 1.0 34.2. pca0 interrupt sources figure 34.3 shows a diagram of the pca interrupt tree . there are eight independent event flags that can be used to generate a pca0 interrupt. they are: the main pca counter overflow flag (cf), which is set upon a 16-bit overflow of the pca0 counter, an inte rmediate overflow flag (covf), which can be set on an overflow from the 8th, 9th, 10th, or 11th bit of t he pca0 counter, and the individual flags for each pca channel (ccf0, ccf1, and ccf2), which are set accord ing to the operation mode of that module. these event flags are always set when the trigger condition occurs. each of these flags can be individually selected to generate a pca0 interrupt, using the corresponding interrupt enable flag (ecf for cf, ecov for covf, and eccfn for each ccfn). pca0 interrupts must be globally enabled before any individual interrupt sources are recognized by the processor. pc a0 interrupts are globally enabled by setting the ea bit and the epca0 bit to logic 1. figure 34.3. pca interrupt block diagram 34.3. capture/compare modules each module can be configured to operate independently in one of six operation modes: edge-triggered capture, software timer, high speed output, frequency output, 8 to 11-bit pulse width modulator, or 16- bit pulse width modulator. each module has special fu nction registers (sfrs) associated with it in the cip-51 system controller. these registers are used to exchange data with a module and configure the module's mode of operation. table 34.2 summarizes the bit settings in th e pca0cpmn and pca0pwm registers used to select the pca capture/compare module?s operating mode. all modules set to use 8, 9, 10, or 11-bit pwm mode must use the same cycle length (8-11 bits). setting the eccfn bit in a pca0cpmn register enables the module's ccfn interrupt. pca0cn c f c r c c f 0 c c f 2 c c f 1 pca0md c i d l e c f c p s 1 c p s 0 c p s 2 0 1 pca module 0 (ccf0) pca module 1 (ccf1) eccf1 0 1 eccf0 0 1 pca module 2 (ccf2) eccf2 pca counter/timer 16- bit overflow 0 1 interrupt priority decoder epca0 0 1 ea 0 1 pca0cpmn (for n = 0 to 2) p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n pca0pwm a r s e l c o v f c l s e l 0 c l s e l 1 e c o v pca counter/timer 8, 9, 10 or 11-bit overflow 0 1 set 8, 9, 10, or 11 bit operation rev. 1.0 287 c8051f70x/71x table 34.2. pca0cpm and pca0pwm bit settings for pca modules operational mode pca0cpmn pca0pwm bit number 76543210765 4:2 1:0 capture triggered by positive edge on cexn xx10000a0xbxxxxx capture triggered by negative edge on cexn xx01000a0xbxxxxx capture triggered by any transition on cexn xx11000a0xbxxxxx software timer xc00100a0xbxxxxx high speed output xc00110a0xbxxxxx frequency output xc00011a0xbxxxxx 8-bit pulse width modulator (note 7) 0 c 0 0 e 0 1 a 0 x b xxx 00 9-bit pulse width modulator (note 7) 0 c 0 0 e 0 1 a d x b xxx 01 10-bit pulse width modulator (note 7) 0 c 0 0 e 0 1 a d x b xxx 10 11-bit pulse width modulator (note 7) 0 c 0 0 e 0 1 a d x b xxx 11 16-bit pulse width modulator 1 c 0 0 e 0 1 a 0 x b xxx xx notes: 1. x = don?t care (no functional difference for individual module if 1 or 0). 2. a = enable interrupts for this module (pca interrupt triggered on ccfn set to 1). 3. b = enable 8th, 9th, 10th or 11th bit overfl ow interrupt (depends on setting of clsel[1:0]). 4. c = when set to 0, the digital comparator is off. for high speed and frequency output modes, the associated pin will not toggle. in any of the pwm modes, this generates a 0% duty cycle (output = 0). 5. d = selects whether the capture/compare register (0) or the auto-reload register (1) for the associated channel is accessed via addresses pca0cphn and pca0cpln. 6. e = when set, a match event will cause the ccfn flag for the associated channel to be set. 7. all modules set to 8, 9, 10 or 11-bit pw m mode use the same cycle length setting. c8051f70x/71x 288 rev. 1.0 34.3.1. edge-triggered capture mode in this mode, a valid transition on the cexn pin ca uses the pca to capture the value of the pca coun- ter/timer and load it into the corresponding module 's 16-bit capture/compar e register (pca0cpln and pca0cphn). the cappn and capnn bits in the pca0cpmn register are used to select the type of transi- tion that triggers the capture: low-to-high transition (p ositive edge), high-to-low transition (negative edge), or either transition (positive or negative edge). when a capture occurs, the capture/compare flag (ccfn) in pca0cn is set to logic 1. an inte rrupt request is generated if the ccfn interrupt for that module is enabled. the ccfn bit is not automatically cleared by hardware when the cpu vectors to the interrupt ser- vice routine, and must be cleared by software. if both cappn and capn n bits are set to logic 1, then the state of the port pin associated wit h cexn can be read directly to de termine whether a rising-edge or fall- ing-edge caused the capture. figure 34.4. pca capture mode diagram note: the cexn input sign al must remain high or lo w for at least 2 system clock cycles to be recognized by the hardware. pca0l pca0cpln pca timebase cexn crossbar port i/o pca0h capture pca0cphn 0 1 0 1 (to ccfn) pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n pca0cn c f c r c c f 0 c c f 2 c c f 1 pca interrupt x 000x x rev. 1.0 289 c8051f70x/71x 34.3.2. software timer (compare) mode in software timer mode, the pca c ounter/timer value is compared to the module's 16-bit capture/compare register (pca0cphn and pca0cpln). when a matc h occurs, the capture/compare flag (ccfn) in pca0cn is set to logic 1. an interr upt request is generated if the ccfn interrupt for that module is enabled. the ccfn bit is not automatically cleared by hardware when the cpu vectors to the interrupt ser- vice routine, and must be cleared by software. setting the ecomn and matn bits in the pca0cpmn regis- ter enables software timer mode. important note about capture/compare registers : when writing a 16-bit value to the pca0 cap- ture/compare registers, the low byte should alwa ys be written first. writing to pca0cpln clears the ecomn bit to 0; writing to pca0cphn sets ecomn to 1. figure 34.5. pca software timer mode diagram match 16-bit comparator pca0h pca0cphn enable pca0l pca timebase pca0cpln 00 00 0 1 x enb enb 0 1 write to pca0cpln write to pca0cphn reset pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n x pca0cn c f c r c c f 0 c c f 2 c c f 1 pca interrupt c8051f70x/71x 290 rev. 1.0 34.3.3. high-speed output mode in high-speed output mode, a module?s associated cexn pin is toggled each time a match occurs between the pca counter and the module's 16- bit capture/compare register (pca0cphn and pca0cpln). when a match occurs, the capture/compar e flag (ccfn) in pca0cn is set to logic 1. an interrupt request is generated if the ccfn interrupt for that module is enabled. the ccfn bit is not auto- matically cleared by hardware when the cpu vectors to the interrupt service routine, and must be cleared by software. setting the togn, matn, and ecomn bi ts in the pca0cpmn register enables the high- speed output mode. if ecomn is cleare d, the associated pin will retain its state, and not toggle on the next match event. important note about capture/compare registers : when writing a 16-bit value to the pca0 cap- ture/compare registers, the low byte should alwa ys be written first. writing to pca0cpln clears the ecomn bit to 0; writing to pca0cphn sets ecomn to 1. figure 34.6. pca high-speed output mode diagram match 16-bit comparator pca0h pca0cphn enable pca0l pca timebase pca0cpln 0 1 00 0x enb enb 0 1 write to pca0cpln write to pca0cphn reset pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n x cexn crossbar port i/o toggle 0 1 togn pca0cn c f c r c c f 0 c c f 2 c c f 1 pca interrupt rev. 1.0 291 c8051f70x/71x 34.3.4. frequency output mode frequency output mode produces a programmable-freq uency square wave on the module?s associated cexn pin. the capture/compare module high byte holds the number of pca clocks to count before the out- put is toggled. the frequency of the square wave is then defined by equation 34.1. equation 34.1. square wave frequency output where f pca is the frequency of the clock selected by the cps2 ? 0 bits in the pca mode register, pca0md. the lower byte of the capture/compare modu le is compared to the pca counter low byte; on a match, cexn is toggled and the offset held in the hi gh byte is added to the matched value in pca0cpln. frequency output mode is enabled by setting the ecomn, togn, and pwmn bits in the pca0cpmn reg- ister. the matn bit should normally be set to 0 in this mode. if the matn bit is set to 1, the ccfn flag for the channel will be set when t he 16-bit pca0 counter an d the 16-bit capt ure/compare register for the chan- nel are equal. figure 34.7. pca frequency output mode f cexn f pca 2 pca0 cphn ? note: a value of 0x00 in the pca0cphn re gister is equal to 256 for this equation. 8-bit comparator pca0l enable pca timebase match pca0cphn 8-bit adder pca0cpln adder enable cexn crossbar port i/o toggle 0 1 togn 000 x pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n x enb enb 0 1 write to pca0cpln write to pca0cphn reset c8051f70x/71x 292 rev. 1.0 34.3.5. 8-bit, 9-bit, 10-bit and 11-bit pulse width modulator modes each module can be used independently to generate a pulse width modulated (pwm) output on its associ- ated cexn pin. the frequency of the output is depe ndent on the timebase for the pca counter/timer, and the setting of the pwm cycle length (8, 9, 10 or 11 -bits). for backwards-compa tibility with the 8-bit pwm mode available on other devices, the 8-bit pwm mode operates slightly different than 9, 10 and 11-bit pwm modes. it is important to note that all channels configured for 8/9/10/11-bit pwm mode will use the same cycle length. it is not possible to configure one channel for 8-bit pwm mode and another for 11- bit mode (for example). however, other pca channels can be configured to pin capture, high-speed out- put, software timer, frequency output, or 16-bit pwm mode independently. 34.3.5.1. 8-bit pulse width modulator mode the duty cycle of the pwm output signal in 8-bit pwm mode is varied using the module's pca0cpln cap- ture/compare register. when the value in the low byte of the pca counter/timer (pca0l) is equal to the value in pca0cpln, the output on th e cexn pin will be set. when the coun t value in pca0l overflows, the cexn output will be reset (see figure 34.8). also, when th e counter/timer low byte (pca0l) overflows from 0xff to 0x00, pca0cpln is reloaded automatically with the value stored in the module?s capture/compare high byte (pca0cphn) without software intervention. setting the ecomn and pwmn bits in the pca0cpmn register, and setting the clsel bits in register pca0pwm to 00b enables 8-bit pulse width modulator mode. if the matn bit is se t to 1, the ccfn flag for the modu le will be set each time an 8-bit comparator match (rising edge) occurs. the covf flag in pca0pwm can be used to detect the overflow (falling edge), which will occur every 256 pca clock cycles. the duty cycle for 8-bit pwm mode is given in equation 34.2. important note about capture/compare registers : when writing a 16-bit value to the pca0 cap- ture/compare registers, the low byte should alwa ys be written first. writing to pca0cpln clears the ecomn bit to 0; writing to pca0cphn sets ecomn to 1. equation 34.2. 8-bit pwm duty cycle using equation 34.2, the largest duty cycle is 100 % (pca0cphn = 0), and the smallest duty cycle is 0.39% (pca0cphn = 0xff). a 0% duty cycle may be generated by clearing the ecomn bit to 0. figure 34.8. pca 8-bit pwm mode diagram duty cycle 256 pca0 cphn ? ?? 256 ----------------------------------- ---------------- = 8-bit comparator pca0l pca0cpln pca0cphn cexn crossbar port i/o enable overflow pca timebase 00x0 x q q set clr s r match pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 0 pca0pwm a r s e l c l s e l 0 c l s e l 1 e c o v x0 0 0 enb enb 0 1 write to pca0cpln write to pca0cphn reset covf c o v f rev. 1.0 293 c8051f70x/71x 34.3.5.2. 9/10/11-bit pu lse width modulator mode the duty cycle of the pwm output signa l in 9/10/11-bit pwm mode should be varied by writing to an ?auto- reload? register, which is dual-mapped into the pc a0cphn and pca0cpln register locations. the data written to define the duty cycle should be right-just ified in the registers. the auto-reload registers are accessed (read or written) when the bit arsel in pca0pwm is set to 1. the capture/compare registers are accessed when arsel is set to 0. when the least-significant n bits of the pca0 coun ter match the value in the associated module?s cap- ture/compare register (pca0cpn), the output on cexn is asserted high. when the counter overflows from the nth bit, cexn is asserted low (see figure 34.9). upon an overflow from the nth bit, the covf flag is set, and the value stored in the module?s auto-reload r egister is loaded into th e capture/compare register. the value of n is determined by the clsel bits in register pca0pwm. the 9, 10 or 11-bit pwm mode is selected by setting the ecomn and pwmn bits in the pca0cpmn regis- ter, and setting the clsel bits in register pca0pwm to the desired cycle length (other than 8-bits). if the matn bit is set to 1, the ccfn fl ag for the module will be set each ti me a comparator match (rising edge) occurs. the covf flag in pca0pwm can be used to detect the overflow (f alling edge), which will occur every 512 (9-bit), 1024 (10-bit) or 2048 (11-bit) pca clock cycles . the duty cycle for 9/10/11-bit pwm mode is given in equation 34.2, where n is the number of bits in the pwm cycle. important note about pca0cphn and pca0cpln registers : when writing a 16-bit value to the pca0cpn registers, the low byte should always be wr itten first. writing to pca0cpln clears the ecomn bit to 0; writing to pca0cphn sets ecomn to 1. equation 34.3. 9, 10, and 11-bit pwm duty cycle a 0% duty cycle may be generated by clearing the ecomn bit to 0. figure 34.9. pca 9, 10 and 11-bit pwm mode diagram duty cycle 2 n pca0 cpn ? ?? 2 n -------------------------------- ----------- - = n-bit comparator pca0h:l (capture/compare) pca0cph:ln (right-justified) (auto-reload) pca0cph:ln (right-justified) cexn crossbar port i/o enable overflow of n th bit pca timebase 00x0 x q q set clr s r match pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 0 pca0pwm a r s e l c l s e l 0 c l s e l 1 e c o v x enb enb 0 1 write to pca0cpln write to pca0cphn reset r/w when arsel = 1 r/w when arsel = 0 set ?n? bits: 01 = 9 bits 10 = 10 bits 11 = 11 bits c o v f c8051f70x/71x 294 rev. 1.0 34.3.6. 16-bit pulse width modulator mode a pca module may also be operated in 16-bit pwm mode. 16-bit pwm mode is independent of the other (8/9/10/11-bit) pwm modes. in this mode, the 16-bit capture/compare module defines the number of pca clocks for the low time of the pwm signal. when the pca counter matches the module contents, the out- put on cexn is asserted high; when the 16-bit counter overflows, cexn is asserted low. to output a vary- ing duty cycle, new value writes should be synchr onized with pca ccfn match interrupts. 16-bit pwm mode is enabled by setting the ecomn, pwmn, and pw m16n bits in the pca0cpmn register. for a vary- ing duty cycle, match interrupts should be enabled (eccfn = 1 and matn = 1) to help synchronize the capture/compar e register writes. if the matn bit is set to 1, the ccfn flag for the module will be set each time a 16-bit comparator match (rising edge) occurs. the cf flag in pca0cn can be used to detect the overflow (falling edge). the duty cycle for 16 -bit pwm mode is given by equation 34.4. important note about capture/compare registers : when writing a 16-bit value to the pca0 cap- ture/compare registers, the low byte should alwa ys be written first. writing to pca0cpln clears the ecomn bit to 0; writing to pca0cphn sets ecomn to 1. equation 34.4. 16-bit pwm duty cycle using equation 34.4, the largest duty cycle is 100% (pca0cpn = 0), and the smallest duty cycle is 0.0015% (pca0cpn = 0xffff). a 0% duty cycle may be generated by clearing the ecomn bit to 0. figure 34.10. pca 16-bit pwm mode duty cycle 65536 pca0 cpn ? ?? 65536 ---------------------------------------------------- - = pca0cpln pca0cphn enable pca timebase 00x0 x pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 1 16-bit comparator cexn crossbar port i/o overflow q q set clr s r match pca0h pca0l enb enb 0 1 write to pca0cpln write to pca0cphn reset rev. 1.0 295 c8051f70x/71x 34.4. register d escriptions for pca0 following are detailed descriptions of the special func tion registers related to the operation of the pca. sfr address = 0xd8; sfr page = all pages; bit-addressable sfr definition 34.1. pca0cn: pca control bit76543210 name cf cr ccf2 ccf1 ccf0 type r/w r/w r r r r/w r/w r/w reset 00000000 bit name function 7cf pca counter/timer overflow flag. set by hardware when the pca counter/timer overflows from 0xffff to 0x0000. when the counter/timer overflow (cf) interrupt is enabled, setting this bit causes the cpu to vector to the pca interrupt service r outine. this bit is not automatically cleared by hardware and must be cleared by software. 6cr pca counter/timer run control. this bit enables/disables the pca counter/timer. 0: pca counter/timer disabled. 1: pca counter/timer enabled. 5:3 unused read = 000b; write = don?t care 2:0 ccf[2:0] pca module n capture/compare flag. these bits are set by hardware when a matc h or capture occurs in the associated pca module n. when the ccfn interrupt is en abled, setting this bi t causes the cpu to vector to the pca interrupt service routine. this bit is not automatically cleared by hardware and must be cleared by software. c8051f70x/71x 296 rev. 1.0 sfr address = 0xed; sfr page = f sfr definition 34.2. pca0md: pca mode bit76543210 name cidl cps2 cps1 cps0 ecf type r/w r r r r/w r/w r/w r/w reset 00000000 bit name function 7cidl pca counter/timer idle control. specifies pca behavior when cpu is in idle mode. 0: pca continues to function normally while the system co ntroller is in idle mode. 1: pca operation is suspended while th e system controller is in idle mode. 6:4 unused read = 000b, write = don't care. 3:1 cps[2:0] pca counter/timer pulse select. these bits select the timebase source for the pca counter 000: system clock divided by 12 001: system clock divided by 4 010: timer 0 overflow 011: high-to-low transitions on eci (max rate = system clock divided by 4) 100: system clock 101: external clock divided by 8 (synchronized with the system clock) 110-111: reserved 0ecf pca counter/timer overflow interrupt enable. this bit sets the masking of the pca co unter/timer overflow (cf) interrupt. 0: disable the cf interrupt. 1: enable a pca counter/timer overflow in terrupt request when cf (pca0cn.7) is set. rev. 1.0 297 c8051f70x/71x sfr address = 0xa1; sfr page = f sfr definition 34.3. pca0pwm : pca pwm configuration bit76543210 name arsel ecov covf clsel[1:0] type r/w r/w r/w r r r r/w reset 00000000 bit name function 7arsel auto-reload register select. this bit selects whether to read and write the normal pca capture/compare registers (pca0cpn), or the auto-reload registers at the same sfr addresses. this function is used to define the reload value for 9, 10, and 11-bit pwm modes. in all other modes, the auto-reload registers have no function. 0: read/write capture/compare registers at pca0cphn and pca0cpln. 1: read/write auto-reload regi sters at pca0cphn and pca0cpln. 6ecov cycle overflow interrupt enable. this bit sets the masking of the cycle overflow flag (covf) interrupt. 0: covf will not gene rate pca interrupts. 1: a pca interrupt will be ge nerated when covf is set. 5covf cycle overflow flag. this bit indicates an overflow of the 8th, 9th, 10th, or 11th bit of the main pca counter (pca0). the specific bit used for this flag depends on the setting of the cycle length select bits. the bit can be set by hardware or software, but must be cleared by soft- ware. 0: no overflow has occurred since the last time this bit was cleared. 1: an overflow has occurred since t he last time this bit was cleared. 4:2 unused read = 000b; write = don?t care. 1:0 clsel[1:0] cycle length select. when 16-bit pwm mode is not selected, th ese bits select the length of the pwm cycle, between 8, 9, 10, or 11 bits. this affects all channels configured for pwm which are not using 16-bit pwm mode. these bits ar e ignored for individual channels config- ured to16-bit pwm mode. 00: 8 bits. 01: 9 bits. 10: 10 bits. 11: 11 bits. c8051f70x/71x 298 rev. 1.0 sfr addresses: pca0cpm0 = 0xda , pca0cpm1 = 0xdb , pca0cpm2 = 0xdc sfr pages: pca0cpm0 = f , pca0cpm1 = f , pca0cpm2 = f sfr definition 34.4. pca0cpmn: pca capture/compare mode bit76543210 name pwm16n ecomn cappn capnn matn togn pwmn eccfn type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7pwm16n 16-bit pulse width modulation enable. this bit enables 16-bit mode when pulse width modulation mode is enabled. 0: 8 to 11-bit pwm selected. 1: 16-bit pwm selected. 6ecomn comparator function enable. this bit enables the comparator function for pca module n when set to 1. 5 cappn capture positive function enable. this bit enables the positive edge capture for pca module n when set to 1. 4 capnn capture negative function enable. this bit enables the negative edge capture for pca module n when set to 1. 3matn match function enable. this bit enables the match function for pca module n when set to 1. when enabled, matches of the pca counter with a module's capture/compare regist er cause the ccfn bit in pca0md register to be set to logic 1. 2togn toggle function enable. this bit enables the toggle function for pca module n when set to 1. when enabled, matches of the pca counter with a module's capture/compare register cause the logic level on the cexn pin to toggle . if the pwmn bit is also set to logic 1, the module oper- ates in frequency output mode. 1pwmn pulse width modulation mode enable. this bit enables the pwm function for pca module n when set to 1. when enabled, a pulse width modulated signal is output on the cexn pin. 8 to 11-bit pwm is used if pwm16n is cleared; 16-bit mode is used if pwm1 6n is set to logic 1. if the togn bit is also set, the module operates in frequency output mode. 0eccfn capture/compare flag interrupt enable. this bit sets the masking of the ca pture/compare flag (ccfn) interrupt. 0: disable ccfn interrupts. 1: enable a capture/compare flag interrupt request when ccfn is set. rev. 1.0 299 c8051f70x/71x sfr address = 0xf9; sfr page = 0 sfr address = 0xfa; sfr page = 0 sfr definition 34.5. pca0l: pca counter/timer low byte bit76543210 name pca0[7:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:0 pca0[7:0] pca counter/timer low byte. the pca0l register holds the low byte (lsb) of the 16-bit pca counter/timer. sfr definition 34.6. pca0h: pca counter/timer high byte bit76543210 name pca0[15:8] type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:0 pca0[15:8] pca counter/timer high byte. the pca0h register holds the high byte (msb) of the 16-bit pca counter/timer. reads of this register will re ad the contents of a ?snapshot ? register, whose contents are updated only when the contents of pca0l are read (see section 34.1). c8051f70x/71x 300 rev. 1.0 sfr addresses: pca0cpl0 = 0xfb , pca0cpl1 = 0xe9 , pca0cpl2 = 0xeb, sfr pages: pca0cpl0 = 0 , pca0cpl1 = 0 , pca0cpl2 = 0, sfr addresses: pca0cph0 = 0xfc , pca0cph1 = 0xea , pca0cph2 = 0xec, sfr pages: pca0cph0 = 0 , pca0cph1 = 0 , pca0cph2 = 0, sfr definition 34.7. pca0cpln: pca capture module low byte bit76543210 name pca0cpn[7:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:0 pca0cpn[7:0] pca capture module low byte. the pca0cpln register holds the low byte (lsb) of the 16-bit capture module n. this register address also allows acce ss to the low byte of the corresponding pca channel?s auto-reload value for 9, 10, or 11-bit pwm mode. the arsel bit in register pca0pwm controls which register is accessed. note: a write to this register will clear the module?s ecomn bit to a 0. sfr definition 34.8. pca0cphn: pca capture module high byte bit76543210 name pca0cpn[15:8] type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:0 pca0cpn[15:8] pca capture module high byte. the pca0cphn register holds the high byte (msb) of the 16-bit capture module n. this register address also allows access to the high byte of the corresponding pca channel?s auto-reload value for 9, 10, or 11-bit pwm mode. the arsel bit in register pca0pwm controls which register is accessed. note: a write to this register will set the module?s ecomn bit to a 1. rev. 1.0 301 c8051f70x/71x 35. c2 interface c8051f70x/71x devices include an on -chip silicon labs 2-wire (c2) d ebug interface to allow flash pro- gramming and in-system debugging with the production pa rt installed in the end a pplication. the c2 inter- face operates using only two pins: a bi-directional da ta signal (c2d), and a clock input (c2ck). see the c2 interface specification for details on the c2 protocol. 35.1. c2 interface registers the following describes the c2 registers necessary to perform flash programming functions through the c2 interface. all c2 registers are accessed through the c2 interface as described in the c2 interface spec- ification. c2 register definition 35.1. c2add: c2 address bit76543210 name c2add[7:0] type r/w reset 00000000 bit name function 7:0 c2add[7:0] c2 address. the c2add register is accessed via the c2 in terface to select the target data register for c2 data read and data write commands. address name description 0x00 deviceid selects the device id register (read only) 0x01 revid selects the revision id register (read only) 0x02 fpctl selects the c2 flash programming control register 0xbf fpdat selects the c2 flash data register 0x96 crc0auto* selects the crc0auto register 0x97 crc0cnt* selects the crc0cnt register 0x91 crc0cn* selects the crc0cn register 0xd9 crc0data* selects the crc0data register 0x95 crc0flip* selects the crc0flip register 0x94 crc0in* selects the crc0in register note: crc registers and functions are described in section ?29. cyclic redundanc y check unit (crc0)? on page 211 . c8051f70x/71x 302 rev. 1.0 c2 address: 0x00 c2 address: 0x01 c2 register definition 35. 2. deviceid: c2 device id bit76543210 name deviceid[7:0] type r/w reset 00011110 bit name function 7:0 deviceid[7:0] device id. this read-only register returns the 8-bit device id: 0x1e (c8051f70x/71x). c2 register definition 35. 3. revid: c2 revision id bit76543210 name revid[7:0] type r/w reset varies varies varies varies varies varies varies varies bit name function 7:0 revid[7:0] revision id. this read-only register returns the 8-bit revision id. for example: 0x00 = revision a. rev. 1.0 303 c8051f70x/71x c2 address: 0x02 c2 address: 0xbf c2 register definition 35.4. fpct l: c2 flash programming control bit76543210 name fpctl[7:0] type r/w reset 00000000 bit name function 7:0 fpctl[7:0] c2 flash programming control register. this register is used to enable flash programming via the c2 interface. to enable c2 flash programming, the following codes must be written in order: 0x02, 0x01. once c2 flash programming is enabled, a system reset must be issued to resume normal operation. c2 register definition 35.5. fp dat: c2 flash programming data bit76543210 name fpdat[7:0] type r/w reset 00000000 bit name function 7:0 fpdat[7:0] c2 flash programming data register. this register is used to pass flash commands, addresses, and data during c2 flash accesses. valid commands are listed below. code command 0x06 flash block read 0x07 flash block write 0x08 flash page erase 0x03 device erase c8051f70x/71x 304 rev. 1.0 35.2. c2ck pin sharing the c2ck pin is shared with the rst signal on this device family. if the rst pin is used by other parts of the system, debugging and pr ogramming the device can still be acco mplished without disr upting the rest of the system. if this is desired, it is normally necessary to add a resistor to isolate the system?s reset line from the c2ck signal. this external resistors would not be necessary for production boards, where debug- ging capabilities are not needed. a typical isolation configurat ion is shown in figure 35.1. figure 35.1. typical c2ck pin sharing the configuration in figure 35.1 assumes the rst pin on the target device is used as an input only. addi- tional resistors may be necessary d epending on the specific application. c2d c2ck rst c2 interface master rev. 1.0 305 c8051f70x/71x d ocument c hange l ist revision 0.5 to revision 1.0 ? updated ?electrical characteristics? on page 47. ? updated ?port input/output? on page 180. revision 0.4 to revision 0.5 ? removed incorrect pin connections in figure 1.4 on page 21 and figure 1.6 on page 23. ? updated specifications in section ?9. electrical characteristics? on page 47. ? updated section ?15. capacitive sense (cs0)? on page 80 for clarity. ? corrected ?cjne a, direct, rel? instruction timing in table 16.1. ? noted that a minimum sysclk speed is requir ed for flash writes or erases in section ?22.1. programming the flash memory? on page 148, and for eeprom writes in section ?23.3. interfacing with the eeprom? on page 155. ? corrected p0.3 overvoltage ca pabilities through out document. revision 0.3 to revision 0.4 ? updated section ?15. capacitive sense (cs0)? on page 80 to reflect revision b enhancements. ? added c8051f716 and c8051f717 devices, package information, and features. ? updated register 19.1, ?hwid: hardware identification byte,? on page 128. ? corrected minor typographical and formatting errors throughout document. revision 0.2 to revision 0.3 ? corrected dimension d in the qfn-48 package specifications. ? updated table 9.1 on page 47. ? updated register 10.1, ?adc0cf: a dc0 configuration,? on page 59. ? updated register 14.3, ?cpt0mx: comparator0 mux selection,? on page 79. ? updated section ?28.1.1. port pins configured for analog i/o? on page 181. ? updated register 35.2, ?deviceid: c2 device id,? on page 302. c8051f70x/71x 306 rev. 1.0 c ontact i nformation silicon laboratories inc. silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademark s or registered trademarks of their respective holders. the information in this document is believed to be accurate in al l respects at the time of publ ication but is subject to change without notice. silicon laboratories assumes no re sponsibility for errors and omissions, and disclaims responsibi lity for any consequen ces resulting from the use of information included herein. additi onally, silicon laboratories assume s no responsibility for the fun ction- ing of undescribed features or parameters. silicon laboratories reserves the right to make changes wi thout further notice. sili con laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpos e, nor does silicon laboratories assu me any liability arising out of the applicati on or use of any product or circuit, and specifi cally disclaims any and all liability , including without limitation consequential or in cidental damages. silicon laboratories product s are not designed, intended, or authorized for us e in applications intended to support or sust ain life, or for any other application in which the failure of the silicon laboratories product could create a si tuation where personal injury or death may occur. should buyer purchase or use silicon laboratories prod ucts for any such unintended or unauthorized application, buyer shall indemnify and hold silicon laboratories harmle ss against all claims and damages. |
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